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| blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor ADSP-BF504/ADSP-BF504f/adsp-bf506f rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features up to 400 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring accepts a range of supply voltag es for internal and i/o opera- tions. see processoroperating conditions on page 25 internal 32m bit flash (available on ADSP-BF504f and adsp-bf506f processors) internal adc (available on adsp-bf506f processor) off-chip voltage regulator interface 88-lead (12 mm 12 mm) lfcsp package for ADSP-BF504 and ADSP-BF504f processors 120-lead (14 mm 14 mm) lqfp package for adsp-bf506f processor memory 68k bytes of l1 sram (processor core-accessible) memory (see table 1 on page 3 for l1 and l3 memory size details) external (interface-accessible) memory controller with glue- less support for internal 32m bit flash and boot rom flexible booting options from internal flash and spi memory or from host devices including spi, ppi, and uart memory management unit providing memory protection peripherals two 32-bit up/down counte rs with rotary support eight 32-bit timers/counters with pwm support two 3-phase 16-bit center-based pwm units 2 dual-channel, fu ll-duplex synchronous serial ports (sports), supporting eight stereo i 2 s channels 2 serial peripheral interface (spi) compatible ports 2 uarts with irda support parallel peripheral interface (ppi), supporting itu-r 656 video data formats removable storage interface (rsi) controller for mmc, sd, sdio, and ce-ata internal adc with 12 channels, 12 bits, and up to 2 msps adc controller module (acm), providing a glueless interface between blackfin processor and internal or external adc controller area network (can) controller 2-wire interface (twi) controller 12 peripheral dmas 2 memory-to-memory dma channels event handler with 52 interrupt inputs 35 general-purpose i/os (gpios), with programmable hysteresis debug/jtag interface on-chip pll capable of frequency multiplication figure 1. processor block diagram sport1C0 voltage regulator interface gpio port f port g port h jtag test and emulation peripheral access bus pwm 1C0 watchdog timer spi1C0 rsi acm ppi can counter1C0 twi boot rom dma access bus interrupt controller dma controller l1 data memory l1 instruction memory 16 dcb eab memory port flash control b uart1C0 deb 32m bit flash timer7C0 adc
rev. a | page 2 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table of contents general description ................................................. 3 portable low-power architecture ............................. 3 system integration ................................................ 3 processor peripherals ............................................. 3 blackfin processor core .......................................... 4 memory architecture ............................................ 5 flash memory ...................................................... 9 dma controllers .................................................. 9 watchdog timer .................................................. 9 timers ............................................................... 9 up/down counters and thumbwheel interfaces ........ 10 3-phase pwm units ............................................ 10 serial ports ........................................................ 10 serial peripheral interface (spi) ports ...................... 11 uart ports (uarts) .......................................... 11 parallel peripheral interface (ppi) ........................... 11 rsi interface ...................................................... 12 controller area network (can) interface ................ 12 twi controller interface ...................................... 13 ports ................................................................ 13 dynamic power management ................................ 13 adsp-bf50x voltage regulation ............................ 15 clock signals ...................................................... 15 booting modes ................................................... 16 instruction set description .................................... 17 development tools .............................................. 17 designing an emulator-compatible processor board (target) ................................... 17 adc and acm interface ....................................... 18 internal adc ..................................................... 19 adc application hints ........................................ 20 related documents .............................................. 20 related signal chains ........................................... 20 signal descriptions ................................................. 21 processorspecifications ......................................... 25 flashspecifications .............................................. 53 adcspecifications ............................................... 54 120-lead lqfp lead assignment . .............................. 72 88-lead lfcsp lead assignment ............................... 75 outline dimensions ................................................ 78 automotive products .............................................. 80 ordering guide ..................................................... 80 revision history 7/11rev. 0 to rev. a numerous small corrections and additions to document. major changes/additions include: revised acm timing diagram, adjusting acm control edge in adc controller module (acm) timing ..................... 47 changed reference output voltage specification in table 47, operating conditions (analog, voltage reference, and logic i/o) .................................................................... 54 added information regarding production release adsp-bf506f products in ordering guide .................. 80 to view product/process change notifications (pcns) related to this data sheet revision, please visit the processor's product page on the www.analog.com website and use the view pcn link. rev. a | page 3 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f general description the adsp-bf50x processors are members of the blackfin ? fam- ily of products, incorporating the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual- mac state-of-the-art signal proc essing engine, the advantages of a clean, orthogonal risc-lik e microprocessor instruction set, and single-instruction, multiple -data (simd) multimedia capa- bilities into a single in struction-set architecture. the adsp-bf50x processors are completely code compatible with other blackfin processors. adsp-bf50x processors offer performance up to 400 mhz and reduced static power con- sumption. differences with respec t to peripheral combinations are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low-power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which provides the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. this capability can resu lt in a substantial reduction in power consumption, compared with just varying the frequency of operation. this allows longer battery life for portable appliances. system integration the adsp-bf50x processors are highly integrated system-on-a- chip solutions for the next generation of embedded industrial, instrumentation, and power/motion control applications. by combining industry-standard interfaces with a high perfor- mance signal processing core, co st-effective applications can be developed quickly, without the ne ed for costly external compo- nents. the system pe ripherals include a watchdog timer; two 32-bit up/down counters with ro tary support; eight 32-bit tim- ers/counters with pwm support; six pairs of 3-phase 16-bit center-based pwm units; two dual-channel, full-duplex syn- chronous serial ports (sports); two serial peripheral interface (spi) compatible ports; two uarts with irda ? support; a par- allel peripheral interface (ppi); a removable storage interface (rsi) controller; an internal ad c with 12 channels, 12 bits, up to 2 msps, and acm controller; a controller area network (can) controller; a 2-wire interface (twi) controller; and an internal 32m bit flash. processor peripherals the adsp-bf50x processors cont ain a rich set of peripherals connected to the core via severa l high-bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see the block diagram on page 1 ). these blackfin processors contain high-speed serial and parallel ports, an interrupt controller for flexib le management of interrupts from the on-chip peripherals or external sour ces, and power management control functions to tailor the performance and power characteristics of the pr ocessor and system to many application scenarios. the sport, spi, uart, ppi, and rsi peripherals are sup- ported by a flexible dma struct ure. there are also separate memory dma channels dedicated to data transfers between the processors various memory sp aces, including boot rom and internal 32m bit synchronous burst flash. multiple on-chip buses running at up to 100 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. the adsp-bf50x processors includ e an interface to an off-chip voltage regulator in support of the processors dynamic power management capability. table 1. processor comparison feature ADSP-BF504 ADSP-BF504f adsp-bf506f up/down/rotary counters 2 2 2 timer/counters with pwm 8 8 8 3-phase pwm units 2 2 2 sports 2 2 2 spis 2 2 2 uarts 2 2 2 parallel peripheral interface 1 1 1 removable storage interface 1 1 1 can 1 1 1 twi 1 1 1 internal 32m bit flash C 1 1 adc control module (acm) 1 1 1 internal adc C C 1 gpios 35 35 35 memory (bytes) l1 instruction sram 16k 16k 16k l1 instruction sram/cache 16k 16k 16k l1 data sram 16k 16k 16k l1 data sram/cache 16k 16k 16k l1 scratchpad 4k 4k 4k l3 boot rom 4k 4k 4k maximum speed grade 1 1 for valid clock combinations, see table 14 , table 15 , table 16 , and table 24 400 mhz maximum system clock speed 100 mhz package options 88-lead lfcsp 88-lead lfcsp 120-lead lqfp rev. a | page 4 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f blackfin processor core as shown in figure 2 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory rev. a | page 5 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the blackfin processor views memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency core-accessible memory as cache or sram and to provide larger, lower cost and perfor- mance interface-accessible memory systems. see figure 3 . the core-accessible l1 memory system is the highest perfor- mance memory available to th e blackfin processor. the interface-accessible memory system, accessed through the external bus interface unit (ebiu), provides access to the inter- nal flash memory and boot rom. the memory dma controller provides high bandwidth data movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (core-accessible) memory the processor has three blocks of core-accessible memory, providing high-bandwidth access to the core. the first block is the l1 instruction memory, consisting of 32k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second core-accessible memory block is the l1 data mem- ory, consisting of 32k bytes of sram, of which 16k bytes may be configured as cache. this me mory block is accessed at full processor speed. the third memory block is 4k bytes of scratchpad sram, which runs at the same speed as the l1 memories, but this memory is only accessible as data sram and cannot be configured as cache memory. external (interface-accessible) memory external memory is accessed via the ebiu memory port. this 16-bit interface provides a gluele ss connection to the internal flash memory and boot rom. internal flash memory ships from the factory in an erased state ex cept for block 0 of the parameter bank. block 0 of the flash memory parameter bank ships from the factory in an unknown state. an erase operat ion should be performed prior to programming this block. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks. one contains the control mmrs for all core functions, and the other contains the registers needed for setup and con- trol of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor and emulation modes and appear as reserved spac e to on-chip peripherals. figure 3. internal/external memory map internal (core-accessible) memory map external (interface-accessible) memory map 0x0000 0000 0x2000 0000 0x2040 0000 0xef00 0000 0xef00 1000 0xff80 0000 0xff80 4000 0xff80 8000 0xffa0 0000 0xffa0 4000 0xffa0 8000 0xffa1 4000 0xffb0 0000 0xffb0 1000 0xffc0 0000 0xffe0 0000 0xffff ffff sync flash (32m bits) * reserved reserved boot rom (4k bytes) l1 data bank a sram (16k bytes) reserved l1 data bank a sram/cache (16k bytes) reserved l1 instruction sram/cache (16k bytes) reserved l1 instruction bank a sram (16k bytes) reserved internal scratchpad ram (4k bytes) reserved system memory mapped registers core memory mapped registers * available on parts with sync flash (f) rev. a | page 6 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f booting the processor contains a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. if the processor is configured to boot from boot rom memory space, the proces- sor starts executing from the on-chip boot rom. for more information, see booting modes on page 16 . event handling the event controller on the proc essor handles all asynchronous and synchronous events to the processor. the processor pro- vides event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioriti zation ensures that servicing of a higher priority event takes pr ecedence over servicing of a lower priority event. the controller provides support for five different types of events: ? emulationan emulation even t causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? resetthis event resets the processor. ? nonmaskable interrupt (nmi)the nmi event can be generated either by the software watchdog timer, by the nmi input signal to the proce ssor, or by software. the nmi event is frequently used as a power-down indicator to initiate an orderly sh utdown of the system. ? exceptionsevents that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interruptsevents that occu r asynchronously to program flow. they are caused by inpu t signals, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return-from-event instruction. when an event is triggered, an interrupt service routine (isr) must save the state of the proce ssor to the supervisor stack. the processor event controller cons ists of two stages: the core event controller (cec) and the system interrupt controller (sic). the core event controller works with the system interrupt controller to prioritize and cont rol all system events. conceptu- ally, interrupts from the peripher als enter into the sic and are then routed directly into the ge neral-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leav ing seven prioritized interrupt inputs to support the peri pherals of the processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controlle r provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (sic_iarx). table 3 describes the inputs into the sic and the default mappings into the cec. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1 reset rst 2 nonmaskable interrupt nmi 3exception evx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general-purpose interrupt 7 ivg7 8 general-purpose interrupt 8 ivg8 9 general-purpose interrupt 9 ivg9 10 general-purpose interrupt 10 ivg10 11 general-purpose interrupt 11 ivg11 12 general-purpose interrupt 12 ivg12 13 general-purpose interrupt 13 ivg13 14 general-purpose interrupt 14 ivg14 15 general-purpose interrupt 15 ivg15 rev. a | page 7 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 3. system interrupt controller (sic) peripheral interrupt source general-purpose interrupt (at reset) peripheral interrupt id default core interrupt id sic registers pll wakeup interrupt ivg7 0 0 iar0 imask0, isr0, iwr0 dma error (generic) ivg7 1 0 iar0 imask0, isr0, iwr0 ppi status ivg7 2 0 iar0 imask0, isr0, iwr0 sport0 status ivg7 3 0 iar0 imask0, isr0, iwr0 sport1 status ivg7 4 0 iar0 imask0, isr0, iwr0 uart0 status ivg7 5 0 iar0 imask0, isr0, iwr0 uart1 status ivg7 6 0 iar0 imask0, isr0, iwr0 spi0 status ivg7 7 0 iar0 imask0, isr0, iwr0 spi1 status ivg7 8 0 iar1 imask0, isr0, iwr0 can status ivg7 9 0 iar1 imask0, isr0, iwr0 rsi mask 0 interrupt ivg7 10 0 iar1 imask0, isr0, iwr0 reserved 11 iar1 imask0, isr0, iwr0 cnt0 interrupt ivg8 12 1 iar1 imask0, isr0, iwr0 cnt1 interrupt ivg8 13 1 iar1 imask0, isr0, iwr0 dma channel 0 (ppi rx/tx) ivg9 14 2 iar1 imask0, isr0, iwr0 dma channel 1 (rsi rx/tx) ivg9 15 2 iar1 imask0, isr0, iwr0 dma channel 2 (sport0 rx) ivg9 16 2 iar2 imask0, isr0, iwr0 dma channel 3 (sport0 tx) ivg9 17 2 iar2 imask0, isr0, iwr0 dma channel 4 (sport1 rx) ivg9 18 2 iar2 imask0, isr0, iwr0 dma channel 5 (sport1 tx) ivg9 19 2 iar2 imask0, isr0, iwr0 dma channel 6 (spi0 rx/tx) ivg10 20 3 iar2 imask0, isr0, iwr0 dma channel 7 (spi1 rx/tx) ivg10 21 3 iar2 imask0, isr0, iwr0 dma channel 8 (uart0 rx) ivg10 22 3 iar2 imask0, isr0, iwr0 dma channel 9 (uart0 tx) ivg10 23 3 iar2 imask0, isr0, iwr0 dma channel 10 (uart1 rx) ivg10 24 3 iar3 imask0, isr0, iwr0 dma channel 11 (uart1 tx) ivg10 25 3 iar3 imask0, isr0, iwr0 can receive ivg11 26 4 iar3 imask0, isr0, iwr0 can transmit ivg11 27 4 iar3 imask0, isr0, iwr0 twi ivg11 28 4 iar3 imask0, isr0, iwr0 port f interrupt a ivg11 29 4 iar3 imask0, isr0, iwr0 port f interrupt b ivg11 30 4 iar3 imask0, isr0, iwr0 reserved 31 iar3 imask0, isr0, iwr0 timer 0 ivg12 32 5 iar4 imask1, isr1, iwr1 timer 1 ivg12 33 5 iar4 imask1, isr1, iwr1 timer 2 ivg12 34 5 iar4 imask1, isr1, iwr1 timer 3 ivg12 35 5 iar4 imask1, isr1, iwr1 timer 4 ivg12 36 5 iar4 imask1, isr1, iwr1 timer 5 ivg12 37 5 iar4 imask1, isr1, iwr1 timer 6 ivg12 38 5 iar4 imask1, isr1, iwr1 timer 7 ivg12 39 5 iar4 imask1, isr1, iwr1 port g interrupt a ivg12 40 5 iar5 imask1, isr1, iwr1 port g interrupt b ivg12 41 5 iar5 imask1, isr1, iwr1 mdma stream 0 ivg13 42 6 iar5 imask1, isr1, iwr1 rev. a | page 8 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f event control the processor provides a very fl exible mechanism to control the processing of events. in the ce c, three registers are used to coordinate and control events. ea ch register is 16 bits wide. ? cec interrupt latch regist er (ilat)indicates when events have been latched. th e appropriate bit is set when the processor has latched the ev ent and is cleared when the event has been accepted into the system. this register is updated automatically by the controller, but it may be writ- ten only when its corresponding imask bit is cleared. ? cec interrupt mask register (imask)controls the masking and unmasking of indivi dual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when a sserted. a cleared bit in the imask register masks the event, preventing the processor from servicing the event even though the event may be latched in the ilat register. th is register ma y be read or written while in supervisor mode. (note that general- purpose interrupts can be globally enabled and disabled with the sti and cli instructions, respectively.) ? cec interrupt pending re gister (ipend)the ipend register keeps track of all nested events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. the sic allows further control of event processing by providing three pairs of 32-bit interrupt cont rol and status re gisters. each register contains a bit, correspo nding to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask register s (sic_imaskx)control the masking and unmasking of each peripheral interrupt event. when a bit is set in these registers, the corresponding peripheral event is unmasked and is forwarded to the cec when asserted. a cl eared bit in these registers masks the corresponding peripheral event, preventing the event from propagating to the cec. ? sic interrupt status registers (sic_isrx)as multiple peripherals can be mapped to a single event, these registers allow the software to determ ine which peripheral event source triggered the interrupt. a set bit indicates that the peripheral is asserting the inte rrupt, and a cleared bit indi- cates that the peripheral is not asserting the event. ? sic interrupt wakeup enable registers (sic_iwrx)by enabling the corresponding bit in these registers, a periph- eral can be configured to wake up the processor should the core be idled or in sleep mode when the event is generated. for more information, see dynamic power management on page 13 . because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recognizes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend output asserted is three core clock cycles; however, the latenc y can be much higher, depend- ing on the activity within and the state of the processor. mdma stream 1 ivg13 43 6 iar5 imask1, isr1, iwr1 software watchdog timer ivg13 44 6 iar5 imask1, isr1, iwr1 port h interrupt a ivg13 45 6 iar5 imask1, isr1, iwr1 port h interrupt b ivg13 46 6 iar5 imask1, isr1, iwr1 acm status interrupt ivg7 47 0 iar5 imask1, isr1, iwr1 acm interrupt ivg10 48 3 iar6 imask1, isr1, iwr1 reserved 49 iar6 imask1, isr1, iwr1 reserved 50 iar6 imask1, isr1, iwr1 pwm0 trip interrupt ivg10 51 3 iar6 imask1, isr1, iwr1 pwm0 sync interrupt ivg10 52 3 iar6 imask1, isr1, iwr1 pwm1 trip interrupt ivg10 53 3 iar6 imask1, isr1, iwr1 pwm1 sync interrupt ivg10 54 3 iar6 imask1, isr1, iwr1 rsi mask 1 interrupt ivg10 55 3 iar6 imask1, isr1, iwr1 reserved 56 through 63 imask1, isr1, iwr1 table 3. system interrupt controller (sic) (continued) peripheral interrupt source general-purpose interrupt (at reset) peripheral interrupt id default core interrupt id sic registers rev. a | page 9 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f flash memory the ADSP-BF504f and adsp-bf506f processors include an on-chip 32m bit (16, multiple bank, burst) flash memory. the features of this memory include: ? synchronous/asynchronous read ? synchronous burst read mode: 50 mhz ? asynchronous/sync hronous read mode ? random access times: 70 ns ? synchronous burst read suspend ? memory blocks ? multiple bank memory array: 4m bit banks ? parameter blocks (top location) ?dual operations ? program erase in one bank while read in others ? no delay between read and write operations ? block locking ? all blocks locked at power-up ? any combination of blocks can be locked or locked down ?security ? 128-bit user programmable otp cells ? 64-bit unique device number ? common flash interface (cfi) ? 100,000 program/erase cycles per block flash memory ships from the factory in an erased state except for block 0 of the parameter bank. block 0 of the flash memory parameter bank ships from the fa ctory in an unknown state. an erase operation should be performed prior to programming this block. dma controllers the processor has multiple, in dependent dma channels that support automated data transfers with minimal overhead for the processor core. dma transf ers can occur between the pro- cessors internal memories and any of its dma-capable peripherals. addition ally, dma transfers ca n be accomplished between any of the dma-capabl e peripherals and external devices connected to the exte rnal memory interface. dma- capable peripherals include th e sports, spi ports, uarts, rsi, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the processor dma controller supports both one-dimensional (1-d) and two-dimensional (2-d) dma transfers. dma trans- fer initialization can be implemen ted from registers or from sets of parameters called descriptor blocks. the 2-d dma capability suppor ts arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 3 2k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types support ed by the processor dma con- troller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a linked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels, whic h are provided for transfers between the various memories of the processor system with minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. watchdog timer the processor includes a 32-bit timer that can be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state through generation of a co re and system reset, nonmask- able interrupt (nmi), or genera l-purpose interrupt, if the timer expires before being reset by so ftware. the programmer initial- izes the count value of the ti mer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. this protects th e system from remaining in an unknown state where software, wh ich would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a reset, the watchdog timer resets both the core and the processor periph erals. after a reset, software can determine whether the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk) at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the processors. eight timers have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri ods of external events. these timers can be synchronized to an external clock input to the sev- eral other associated pf pins, to an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the two uarts to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. rev. a | page 10 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the eight general-purpose programmable timers, a ninth timer is also provided. this extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. up/down counters and thumbwheel interfaces two 32-bit up/down counters are provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. the counters can also operate in general-purpose up/down co unt modes. then, count direc- tion is either controlled by a l evel-sensitive input pin or by two edge detectors. a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins ha ve a programmable debouncing circuit. internal signals forwarded to each timer unit enable these tim- ers to measure the intervals between count events. boundary registers enable auto-zero operat ion or simple system warning by interrupts when programmabl e count values are exceeded. 3-phase pwm units the two/dual 3-phase pwm generation units each feature: ? 16-bit center-based pwm generation unit ?programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ? twos-complement implementation which permits smooth transition to full on and full off states ? possibility to synchronize th e pwm generation to either externally-generated or inte rnally-generated synchroniza- tion pulses ? special provisions for bd cm operation (crossover and output enable functions) ? wide variety of special switch ed reluctance (sr) operating modes ? output polarity and clock gating control ? dedicated asynchronous pwm shutdown signal each pwm block integrates a flexible and programmable 3-phase pwm waveform generato r that can be programmed to generate the required switchin g patterns to drive a 3-phase voltage source inverter for ac induction motor (acim) or permanent magnet synchronous motor (pmsm) control. in addition, the pwm block contains special functions that considerably simplify the generation of the required pwm switching patterns for control of the electronica lly commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for swit ched reluctance motors (srm). the six pwm output signals (per pwm unit) consist of three high-side drive signals (pwmx_ah, pwmx_bh, and pwmx_ch) and three low-side drive signals (pwmx_al, pwmx_bl, and pwmx_cl). the polarity of the generated pwm signal can be set with software, so that either active hi or active lo pwm patterns can be produced. the switching frequency of the generated pwm pattern is pro- grammable using the 16-bit pwm_tm register. the pwm generator can operate in single update mode or double update mode. in single update mode, the duty cycle values are pro- grammable only once per pwm pe riod, so that the resultant pwm patterns are symmetrical about the midpoint of the pwm period. in the double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mode, it is po ssible to produce asymmetrical pwm patterns that produce lowe r harmonic distortion in 3-phase pwm inverters. pulses synchronous to the switch ing frequency can be generated internally and output on the pwmx_sync pin. the pwm unit can also accept externally generated synchronization pulses through pwmx_sync. each pwm unit features a dedi cated asynchronous shutdown pin, pwmx_trip , which (when brought low) instantaneously places all six pwm outputs in the off state. serial ports the processors incorporate two dual-channel synchronous serial ports (sport0 and sport1) for serial and multiproces- sor communications. the spor ts support the following features: ?i 2 s capable operation. ? bidirectional operationeach sport has two sets of inde- pendent transmit and receive pins, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive portseach port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clockingeach transmit and re ceive port can either use an external serial clock or gene rate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word lengtheach sport supports serial data words from 3 to 32 bits in length, transferred most significant bit first or least significant bit first. ? framingeach transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardwareeach sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. rev. a | page 11 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f ? dma operations with single-cycle overheadeach sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interruptseach transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through dma. ? multichannel capabilityeac h sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) ports the adsp-bf50x processors ha ve two spi-compatible ports that enable the processor to communicate with multiple spi- compatible devices. the spi interface uses three pins for transferring data: two data pins mosi (master output-slave input) and miso (master input-slave output) and a clock pin, serial clock (sck). an spi chip select input pin (spix_ss ) lets other spi devices select the processor, and three spi chip se lect output pins (spix_sel3C1 ) let the processor select other spi devices. the spi select pins are reconfigured general-purpose i/ o pins. using these pins, the spi port provides a full-duplex, synchronous serial interface, which supports both master/s lave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are programmable, and it has an integrated dma channel, configurable to support transmit or receive data streams. the spis dma channel can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud register contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports (uarts) the adsp-bf50x blackfin proce ssors provide two full-duplex universal asynchronous receiv er/transmitter (uart) ports. each uart port provides a simplified uart interface to other peripherals or hosts, enabli ng full-duplex, dma-supported, asynchronous transfers of serial data. a uart port includes support for five to eight data bits; one or two stop bits; and none, even, or odd parity. each uart port supports two modes of operation: ? pio (programmed i/o). the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) . the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. ea ch uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their relati vely low service rates. flexi- ble interrupt timing options are available on the transmit side. each uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk ) bits per second. ? supporting data formats from 7 to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as where the 16-bit uart diviso r comes from the uartx_dlh register (most significant 8 bits ) and uartx_dll register (least significant eight bits), and the edbo is a bit in the uartx_gctl register. in conjunction with the general- purpose timer functions, auto- baud detection is supported. the uarts feature a pair of uax_rts (request to send) and uax_cts (clear to send) signals fo r hardware flow purposes. the transmitter hardware is automatically pr evented from sending further data when the uax_cts input is de-asserted. the receiver can automatica lly de-assert its uax_rts output when the enhanced receive fifo exceeds a certain high-water level. the capabilities of the uarts are further extended with support for the infrar ed data association (irda?) serial infra- red physical layer link specification (sir) protocol. parallel peripheral interface (ppi) the processor provides a parallel peripheral interface (ppi) that can connect directly to parallel a/d and d/a converters, video encoders and decoders, and othe r general-purpose peripherals. the ppi consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. spi clock rate f sclk 2 spi_baud ----------------------------------- - = uart clock rate f sclk 16 1edbo ? () uart_divisor ----------------------------------------------------------------------- - = rev. a | page 12 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general-purpose mode, the ppi provides half-duplex, bidirectional data tr ansfer with up to 16 bits of data. up to three frame synchr onization signals are also pro- vided. in itu-r 656 mode, th e ppi provides half-duplex bidirectional transfer of 8- or 10-bit video data. additionally, on-chip decode of embedded start-of-line (sol) and start-of- field (sof) preamble packets is supported. general-purpose mode descriptions the general-purpose modes of th e ppi are intended to suit a wide variety of data capture and transmission applications. three distinct submodes are supported: ? input modeframe syncs and data are inputs into the ppi. ? frame capture modeframe syncs are outputs from the ppi, but data are inputs. ? output modeframe syncs and data are outputs from the ppi. input mode input mode is intended for adc applications, as well as video communication with hardware sign aling. in its simplest form, ppi_fs1 is an external frame sync input that controls when to read data. the ppi_delay mmr allows for a delay (in ppi_clk cycles) between receptio n of this frame sync and the initiation of data reads. the nu mber of input data samples is user programmable and defined by the contents of the ppi_count register. the ppi supports 8-bit and 10-bit through 16-bit data, programmable in the ppi_control register. frame capture mode frame capture mode allows the video source(s) to act as a slave (for frame capture for example) . the adsp-bf50x processors control when to read from the video source(s). ppi_fs1 is an hsync output and ppi_fs2 is a vsync output. output mode output mode is used for transmitting video or other data with up to three output frame syncs. typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. itu-r 656 mode descriptions the itu-r 656 modes of the ppi ar e intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct submodes are supported: ? active video only mode ? vertical blanking only mode ? entire field mode active video mode active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. the ppi does not read in any da ta between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. afte r synchronizing to the start of field 1, the ppi ignores incoming samples until it sees an sav code. the user specifies the number of active video lines per frame (in ppi_count register). vertical blanking interval mode in this mode, the ppi only transfers vertical blanking interval (vbi) data. entire field mode in this mode, the entire incoming bit stream is read in through the ppi. this includes active vide o, control preamble sequences, and ancillary data that may be embedded in horizontal and ver- tical blanking intervals. data transfer starts immediately after synchronization to field 1. data is transferred to or from the synchronous channels through eight dma engines that work autonomously from the processor core. rsi interface the removable storage interface (r si) controller acts as the host interface for multimedia cards (mmc), secure digital memory cards (sd), secure digital input/output cards (sdio), and ce- ata hard disk drives. the followi ng list describes the main fea- tures of the rsi controller. ? support for a single mmc, sd memory, sdio card or ce- ata hard disk drive ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit, and 8-bit mmc modes ? support for 4-bit and 8-bi t ce-ata hard disk drives ? a ten-signal external interface with clock, command, and up to eight data lines ? card detection using one of the data signals ? card interface clock generation from sclk ? sdio interrupt and read wait features ? ce-ata command completion signal recognition and disable controller area network (can) interface the adsp-bf50x processors provide a can controller that is a communication controller implem enting the controller area network (can) v2.0b protocol. this protocol is an asynchro- nous communications protocol used in both industrial and automotive control systems. ca n is well suited for control applications due to its capability to communicate reliably over a network since the protocol inco rporates crc checking, message error tracking, and fault node confinement. the can controller is based on a 32-entry mailbox ram and supports both the stan dard and extended identifier (id) mes- sage formats specified in the can protocol specification, revision 2.0, part b. rev. a | page 13 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f each mailbox consists of eight 16-bit data words. the data is divided into fields, which includes a message identifier, a time stamp, a byte count, up to 8 bytes of data, and several control bits. each node monitors the messages being passed on the net- work. if the identifier in the transmitted message matches an identifier in one of its mailboxes, the module knows that the message was meant for it, passes the data into its appropriate mailbox, and signals the processo r of message arrival with an interrupt. the can controller can wake up the processor from sleep mode upon generation of a wake-up even t, such that the processor can be maintained in a low-power mode during idle conditions. additionally, a can wake-up event can wake up the on-chip internal voltage regulator from the powered-down hibernate state. the electrical characteristics of each network connection are very stringent. theref ore, the can interface is typically divided into two parts: a controller and a transceiver. this allows a sin- gle controller to support differ ent drivers and can networks. the adsp-bf50x can module repr esents the controller part of the interface. this modules ne twork i/o is a single transmit output and a single receive input, which connect to a line transceiver. the can clock is derived from the processor system clock (sclk) through a programmable divider and therefore does not require an additional crystal. twi controller interface the processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is co mpatible with the widely used i 2 c ? bus standard. the twi module offers the capa bilities of simultaneous master and slave op eration, support for both 7-bit addressing and multimedia data arbitration. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at sp eeds up to 400k bits/sec. the twi interface pins are compat ible with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. ports because of the rich set of periph erals, the processor groups the many peripheral signals to thre e portsport f, port g, and port h. most of the associated pi ns are shared by multiple sig- nals. the ports function as multiplexer controls. general-purpose i/o (gpio) the processor has 35 bidirectional, general-purpose i/o (gpio) pins allocated across three se parate gpio modulesportfio, portgio, and porthio, associated with port f, port g, and port h, respectively. each gpio -capable pin shares functional- ity with other processor peripher als via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output nor input drivers are active by default. each general- purpose port pin can be individ- ually controlled by mani pulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C the processor employs a write one to modify mechanism that allows any combi- nation of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. four control registers ar e provided. one register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. reading the gpio status register allows software to interrogate the sense of the pins. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each indi vidual gpio pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual pin values, one gpio interrupt mask register sets bits to enable interrupt function, an d the other gpio interrupt mask register clears bits to disable interrupt function. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C the two gpio inter- rupt sensitivity registers specif y whether individual pins are level- or edge-sensitive an d specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. dynamic power management the processor provides five oper ating modes, each with a differ- ent performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissi- pation. when configured for a 0 volt core supply voltage, the processor enters the hibernate stat e. control of clocking to each of the processor peripherals al so reduces power consumption. see table 4 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropri ately configured l1 memories. rev. a | page 14 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f in the active mode, it is possible to disable the control input to the pll by setting the pll_off bit in the pll control register. this register can be accessed wi th a user-callable routine in the on-chip rom called bfrom_syscontrol(). if disabled, the pll control input must be re-enabled before transitioning to the full-on or sleep modes. for more information about pl l controls, see the dynamic power management chapter in the adsp-bf50x blackfin pro- cessor hardware reference . sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally, an external event wakes up the processor. when in the sleep mode, asserting a wakeup enabled in the sic_iwrx regis- ters causes the processor to sens e the value of the bypass bit in the pll control register (pll_ctl ). if bypass is disabled, the processor transitions to the full on mode. if bypass is enabled, the processor transitions to the active mode. dma accesses to l1 memory are not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals may still be running but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset pin (reset ). assertion of reset while in deep sleep mode causes the pr ocessor to transition to the full on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and to all of the peripherals (sclk). this setti ng sets the internal power sup- ply voltage (v ddint ) to 0 v to provide the lowest static power dissipation. any critical information stored internally (for example, memory contents, register contents, and other infor- mation) must be written to a non-volatile storage device prior to removing power if the processo r state is to be preserved. writing 0 to the hibernate bit causes ext_wake to transi- tion low, which can be used to signal an external voltage regulator to shut down. since v ddext can still be supplied in this mode, all of the exter- nal pins three-state, unless othe rwise specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. the processor can be woken up by asserting the reset pin. all hibernate wakeup events initiate the hardware reset sequence. individual sources are enabled by the vr_ctl register. the ext_wake signal indicates the occurrence of a wakeup event. as long as v ddext is applied, the vr_ctl register maintains its state during hibernation. all other internal registers and memo- ries, however, lose their content in the hibernate state. power savings as shown in table 5 , the processor supports three different power domains, which maximizes flexibility while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from other i/o, the processor can take advan- tage of dynamic power management without affecting the other i/o devices. there are no sequen cing requirements for the vari- ous power domains, but all domains must be powered according to the appropriate processorspecifications table for processor operating conditions; even if the feature/peripheral is not used. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, these power sa vings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. table 4. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off table 5. power domains power domain power supply all internal logic, except memory v ddint flash memory v ddflash all other i/o v ddext adc digital supply 1 (logic, i/o) 1 on adsp-bf506f processor only. dv dd , v drive adc analog supply 1 av dd power savings factor f cclkred f cclknom -------------------------- v ddintred v ddintnom ------------------------------- - ?? ?? 2 t red t nom -------------- - ? ? ? ? = rev. a | page 15 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f where the variables in the equations are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage t nom is the duration running at f cclknom t red is the duration running at f cclkred adsp-bf50x voltage regulation the adsp-bf50x processors requir e an external voltage regula- tor to power the v ddint domain. to reduce standby power consumption, the external voltage regulator can be signaled through ext_wake to remove power from the processor core. this signal is high-true for power-up and may be connected directly to the low-true shut-down input of many common regulators. while in the hibernate state, all external supplies (v ddext , v ddflash ) can still be applied, elimin ating the need for external buffers. the external voltage re gulator can be activated from this power down state by asserting the reset pin, which then initiates a boot sequence. ext_wake indicates a wakeup to the external voltage regulator. the power good (pg ) input signal allows the processor to start only after the internal voltage has reached a chosen level. in this way, the startup time of the external regulator is detected after hibernation. for a complete description of the power good functionality, refer to the adsp-bf50x blackfin processor hard- ware reference . clock signals the processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl-compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the processor includes an on-chip oscilla- tor circuit, an external crysta l may be used. for fundamental frequency operation, us e the circuit shown in figure 4 . a paral- lel-resonant, fundamental freq uency, microprocessor-grade crystal is connected across th e clkin and xtal pins. the on- chip resistance between clkin and the xtal pin is in the 500 k range. further parallel resi stors are typically not recom- mended. the two capacitors and the series resistor shown in figure 4 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 4 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufact urer. the user should verify the customized values based on careful investigations on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in figure 4 . a design procedure fo r third-overtone oper- ation is discussed in detail in (ee-168) using third overtone crystals with the adsp-218x dsp on the analog devices web- site ( www.analog.com )use site search on ee-168. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 5 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programm able multiplication factor (bounded by specified minimum and maximum vco frequen- cies). the default multiplier is 6, but it can be modified by a software instruction sequence. on-the-fly frequency changes can be effected by simply writing to the pll_div register. th e maximum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext ; the vco is always permitted to run up to the cclk frequency specified by the parts speed grade. the extclk pin can be configured to output either th e sclk frequency or the input buffered clkin frequency, called clkbuf. when configured to output sclk (clkout), the extclk pin acts as a refer- ence signal in many timing specifications. while active by default, it can be disabled using the ebiu_amgctl register. % power savings 1 power savings factor ? () 100% = figure 4. external crystal connections clkin clkout (sclk) xtal select clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18 pf should be treated as a maximum, and the suggested resistor value should be reduced to 0 . 18 pf * en 18 pf * 330 * blackfin processor 560 extclk en rev. a | page 16 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency both depends on the parts speed grade and depends on the applied v ddint voltage. see table 14 for details. the maximal system clock rate (sclk) depends on the applied v ddint and v ddext voltages (see table 16 ). booting modes the processor has several mechanisms (listed in table 8 ) for automatically loading internal and external memory after a reset. the boot mode is define d by the bmode input pins dedi- cated to this purpose. there are two categories of boot modes. in master boot modes, the proc essor actively loads data from parallel or serial memories. in slave boot modes, the processor receives data from external host devices. the boot mode s listed in table 8 provide a number of mecha- nisms for automatically loading the processors internal and external memories after a reset. by default, all boot modes use the slowest meaningful configuration settings. default settings can be altered via the initialization code feature at boot time. some boot modes require a boot host wait (hwait) signal, which is a gpio output signal th at is driven and toggled by the boot kernel at boot time. if pulled high through an external pull- up resistor, the hwait signal be haves active high and will be driven low when the processor is ready for data. conversely, when pulled low, hwait is driven high when the processor is ready for data. when the boot sequence completes, the hwait pin can be used for other purp oses. the bmode pins of the reset configuration register, sa mpled during power-on resets and software-initiated resets, implement the modes shown in table 8 . ? idle state / no boot (bmode = 0x0)in this mode, the boot kernel transitions the pr ocessor into idle state. the processor can then be controlled through jtag for recov- ery, debug, or other functions. ? boot from stacked parallel flash in 16-bit asynchronous mode (bmode = 0x1)in this mode, conservative timing parameters are used to communicate with the flash device. the boot kernel communicates with the flash device asynchronously. ? boot from stacked parallel flash in 16-bit synchronous mode (bmode = 0x2)in this mode, fast timing parame- ters are used to communicate with the flash device. the boot kernel configures the flash device for synchronous burst communication and boots from the flash synchronously. figure 5. frequency mo dification methods table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 50 50 0110 6:1 300 50 1010 10:1 400 40 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 pll 0.5 to 64 1to15 1,2,4,8 vco clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk sclk cclk table 8. booting modes bmode2C0 description 000 idle/no boot 001 boot from internal parallel flash in async mode 1 1 this boot mode a pplies to ADSP-BF504f and adsp-bf506f processors only. 010 boot from internal parallel flash in sync mode 1 011 boot through spi0 master from spi memory 100 boot through spi0 sla ve from host device 101 boot through ppi from host 110 reserved 111 boot through uart0 slave from host device rev. a | page 17 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f ? boot from serial spi memory, eeprom or flash (bmode = 0x3)8-, 16-, 24-, or 32-bit addressable devices are supported. the processor uses the pf13 gpio pin to select a single spi eep rom/flash device (connected to the spi0 interface) and submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is de tected. pull-up resistors are required on the spi0_sel1 and miso pins. by default, a value of 0x85 is written to the spi_baud register. ? boot from spi host device (bmode = 0x4)the proces- sor operates in spi slave mode and is configured to receive the bytes of the ldr file from an spi host (master) agent. the hwait signal must be inte rrogated by the host before every transmitted byte. a pull-up resistor is required on the spi0_ss input. a pull-down on th e serial clock (sck) may improve signal quality and booting robustness. ? boot from ppi host device (bmode = 0x5)the proces- sor operates in ppi slave mode and is configured to receive the bytes of the ldr file from a ppi host (master) agent. ? boot from uart0 host on port g (bmode = 0x7) using an autobaud handshake sequence, a boot-stream for- matted program is downloaded by the host. the host selects a bit rate within the uart clocking capabilities. when performing the autobaud detection, the uart expects an @ (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the ua0_rx pin to deter- mine the bit rate. the uart then replies with an acknowledgement composed of 4 bytes (0xbf, the value of uart0_dll, the value of uart0_dlh, then 0x00). the host can then download the boot stream. the processor deasserts the ua0_rts output to hold off the host; ua0_cts functionality is not enabled at boot time. for each of the boot modes, a 16 byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the address stored in the evt1 register. the boot kernel differentiates be tween a regular hardware reset and a wakeup-from-hibernate even t to speed up booting in the later case. bits 6-4 in the syst em reset configuration (syscr) register can be used to bypass the pre-boot routine and/or boot kernel in case of a software reset. they can also be used to simu- late a wakeup-from-hibernate boot in the software reset case. the boot process can be further customized by initialization code. this is a piece of code that is loaded and executed prior to the regular application boot. typically, this is used to speed up booting by managing the pll, clock frequencies, wait states, or serial bit rates. the boot rom also features c- callable functions that can be called by the user application at run time. this enables second- stage boot or boot management schemes to be implemented with ease. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to provide a flexible, densely encode d instruction set that compiles to a very small final memory size. the instruction set also provides fully featured multifunct ion instructions that allow the programmer to use many of the processor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruct ion set is very efficient when compiling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which ta kes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mc u features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store mo dified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16-bit and 32-bit instru ctions (no mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the processor is supported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++ ? devel- opment environment. the same emulator hardware that supports other blackfin processors also fully emulates the adsp-bf50x processors. ez-kit lite evaluation board for evaluation of adsp-bf50x processors, use the ez-kit lite ? boards soon to be available from analog devices. when these evaluation kits are available, order using part number adzs-bf506-ezlite. the boar ds come with on-chip emulation capabilities and is equipped to enable software development. multiple daughter cards will be available. designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog de vices has supplied an ieee 1149.1 rev. a | page 18 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f jtag test access port (tap) on each jtag processor. the emulator uses the tap to access th e internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the processor must be halted to se nd data and commands, but once an operation has been completed by the emulator, the processor system is set running at fu ll speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (ee-68) analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. adc and acm interface this section describes the ad c and acm interface. system designers should also consult the adsp-bf50x blackfin proces- sor hardware reference for additional information. the adc control module (acm) provides an interface that synchronizes the controls betw een the processor and the inter- nal analog-to-digital converte r (adc) module. the acm is available on the ADSP-BF504, ADSP-BF504f, and adsp-bf506f processors, and th e adc is available on the adsp-bf506f processor only. th e analog-to-digital conver- sions are initiated by the proc essor, based on external or internal events. the acm allows for flexible sche duling of sampling instants and provides precise sampli ng signals to the adc. the acm synchronizes the adc conversion process; generat- ing the adc controls, the adc conversion start signal, and other signals. the actual data acquisition from the adc is done by the sport peripherals. the serial interface on the adc allows the part to be directly connected to the adsp-b f504, ADSP-BF504f, and adsp-bf506f processors using serial interface protocols. figure 6 shows how to connect an external adc to the acm and one of the tw o sports on the ADSP-BF504 or ADSP-BF504f processors. the adc is integrated into the adsp-bf506f product. figure 7 shows how to connect the internal adc to the acm and to one of the two sports on the adsp-bf506f processor. the ADSP-BF504, ADSP-BF504f , and adsp-bf506f proces- sors interface directly to the adc without any glue logic required. the availability of se condary receive registers on the serial ports of the blackfin proce ssors means only one serial port figure 6. adc (external), acm, and sport connections figure 7. adc (internal), acm, and sport connections sportx drxsec drxpri rclkx rfsx adc (external) d out b d out a adsclk cs range sgl/ diff a[2:0] acm cs aclk acm_range acm_sgldiff acm_a[2:0] ADSP-BF504 / ADSP-BF504f sport select mux sportx drxsec drxpri rclkx rfsx adc (internal) d out b d out a adsclk cs range sgl/ diff a[2:0] acm cs aclk acm_range acm_sgldiff acm_a[2:0] adsp-bf506f sport select mux rev. a | page 19 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f is necessary to re ad from both d out pins simultaneously. figure 7 ( adc (internal), acm, and sport connections ) shows both d out a and d out b of the adc connected to one of the processors serial ports. th e sportx receive configuration 1 register and sportx receive configuration 2 register should be set up as outlined in table 9 ( the sportx receive configu- ration 1 register (sportx_rcr1) ) and table 10 ( the sportx receive configuration 2 register (sportx_rcr2) ). note: the sport must be enabled with the following set- tings: external clock, external frame sync, and active low frame sync. to implement the powe r-down modes, slen should be set to 1001 to issue an 8-bit sclk burs t. a blackfin driver for the adc is available to download at www.analog.com . internal adc an adc is integrated into the adsp-bf506f product. all adc signals are connected out to package pins to enable maximum interconnect flexibility in mixed signal applications. the internal adc is a dual, 12-bit, high speed, low power, suc- cessive approximation adc that operates from a single 2.7 v to 5.25 v power supply and features throughput rates up to 2 msps. the device contains tw o adcs, each preceded by a 3-channel multiplexer, and a low noise, wide bandwidth track- and-hold amplifier that can handle input frequencies in excess of 30 mhz. figure 8 shows the functional block diagram of the internal adc. the adc features include: ? dual 12-bit, 3-channel adc ? throughput rate: up to 2 msps ? specified for dv dd and av dd of 2.7 v to 5.25 v ? pin-configurable analog inputs ? 12-channel single-ended inputs or ? 6-channel fully differential inputs or ? 6-channel pseudo differential inputs ? accurate on-chip voltage reference: 2.5 v ? dual conversion with read 437.5 ns, 32 mhz adsclk ? high speed serial interface ?spi-/qspi tm -/microwire tm -/dsp-compatible ? low power shutdown mode the conversion process and data acquisition use standard con- trol inputs allowing easy inte rfacing to microprocessors or dsps. the input signal is samp led on the falling edge of cs ; con- version is also initiated at this point. the conversion time is determined by the adsclk freq uency. there are no pipelined delays associated with the part. the internal adc uses advanced design techniques to achieve very low power dissipation at hi gh throughput ra tes. the part also offers flexible power/thro ughput rate management when operating in normal mode as the quiescent current consump- tion is so low. the analog input range for the part can be selected to be a 0 v to v ref (or 2 v ref ) range, with either straight binary or twos complement output coding. the internal adc has an on-chip 2.5 v reference that can be over driven when an external refer- ence is preferred. table 9. the sportx receive configuration 1 register (sportx_rcr1) setting description rckfe = 1 sample data with rising edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 0 external rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 0 external receive clock rspen = 1 receive enabled tfsr = rfsr = 1 table 10. the sportx receive configuration 2 register (sportx_rcr2) setting description rxse = 1 secondary side enabled slen = 1111 16-bit data-word (or may be set to 1101 for 14-bit data-word) figure 8. adc (internal) functional block diagram 12-bit successive approximation adc d out a output drivers control logic t/h buf v a1 v a2 v a3 v a4 v a5 v a6 mux ref adc v drive ref select d cap a av dd dv dd buf d out b output drivers 12-bit successive approximation adc t/h v b1 v b2 v b3 v b4 v b5 v b6 mux agnd agnd agnd d cap b dgnd dgnd cs adsclk range sgl/diff a0 a1 a2 rev. a | page 20 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f additional highlights of the internal adc include: ? two complete adc function s allow simultaneous sam- pling and conversion of two channelseach adc has three fully/pseudo differential pairs, or six single-ended channels, as programmed. the conversion result of both channels is simultaneously avai lable on separate data lines, or in succession on one data line if only one serial connec- tion is available. ? high throughput with low power consumption ? the internal adc offers both a standard 0 v to v ref input range and a 2 v ref input range. ? no pipeline delaythe part features two st andard succes- sive approximation adcs with accurate control of the sampling instant via a cs input and once off conversion control. adc application hints the following sections provide application hints for using the adc. grounding and layout considerations the analog and digital supplies to the adc are independent and separately pinned out to minimi ze coupling between the analog and digital sections of the d evice. the printed circuit board (pcb) that houses the adc should be designed so that the ana- log and digital sections are separated and confined to certain areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. all agnd pins should be sunk in the agnd plane. digital and analog ground planes should be joined in only one place. if th e adc is in a system where multi- ple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the adc. avoid running digital lines under the device as this couples noise onto the die. avoid running digital lines in the area of the agnd pad as this couples noise onto the adc die and into the agnd plane. the power supply li nes to the adc should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shield ed with digital ground, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feed through within the board, traces on opposite sides of the boar d should run at right angles to each other. good decoupling is also import ant. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effect ive series resistance (esr) and effective series inductance (esi ), such as the common ceramic types or surface-mount types. th ese low esr and esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. related documents the following publications that describe the adsp-bf50x pro- cessors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf50x blackfin proc essor hardware reference (vol- umes 1 and 2) ? blackfin processor programming reference ? adsp-bf50x blackfin processor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http:\\www.analog.com\signalchains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques rev. a | page 21 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f signal descriptions signal definitions for the adsp-b f50x processors are listed in table 11 . all pins for the adc (a dsp-bf506f processor only) are listed in table 12 . in order to maintain maximum function and reduce package size and pin count, some pins have multiple, multiplexed func- tions. in cases where pin function is reconfigurable, the default state is shown in plain text, wh ile the alternate functions are shown in italics. during and immediately after rese t, all processor signals (not adc signals) are three-stated with the following exceptions: ext_wake is driven high and xtal is driven in conjunction with clkin to create a crystal oscillator circuit. during hibernate, all signals are three- stated with the following excep- tions: ext_wake is driven low and xtal is driven to a solid logic level. during and immediately after reset, all i/o pins have their input buffers disabled until enabled by user software with the excep- tion of the pins that need pull- ups or pull-downs, as noted in table 11 . adding a parallel termination to clkout may prove useful in further enhancing signal integrit y. be sure to verify over- shoot/undershoot and signal integrity specifications on actual hardware. table 11. processorsignal descriptions signal name type function driver type port f: gpio and multiplexed peripherals pf0 /tsclk0/ua0_rx/tmr6/cud0 i/o gpio /sport0txserialclk/uart0 rx/timer6/count up dir0 c pf1 /rsclk0/ua0_tx/tmr5/cdg0 i/o gpio /sport0rxserialclk/uart0 tx/timer5/count down dir 0 c pf2 /dt0pri/pwm0_bh/ppi_d8/czm0 i/o gpio /sport0txpridata/pwm0 drive b hi/ppidata8/counter zero marker 0 c pf3 /tfs0/pwm0_bl/ppi_d9/cdg0 i/o gpio /sport0txframesync/pwm0 drive b lo/ppidata9/count down dir 0 c pf4 /rfs0/pwm0_ch/ppi_d10/taclk0 i/o gpio /sport0rxframesync/pwm0drive c hi/ppidata10/alttimerclk0 c pf5 /dr0pri/pwm0_cl/ppi_d11/taclk1 i/o gpio /sport0prirxdata/pwm0 drive c lo/ppidata11/alttimerclk1 c pf6 /ua1_tx/pwm0_trip /ppi_d12 i/o gpio /uart1tx/pwm0trip/ppidata12 c pf7 /ua1_rx/pwm0_sync/ppi_d13/taci3 i/o gpio /uart1rx/pwm0 sync/ppidata13/alt capture in3 c pf8 /ua1_rts /dt0sec/ppi_d7 i/o gpio /uart1 rts/sport0 tx sec data/ppi data 7 c pf9 /ua1_cts /dr0sec/ppi_d6/czm0 i/o gpio /uart1cts/sport0 sec rx data/ppidata6/counter zero marker0 c pf10 /spi0_sck/tmr2/ppi_d5 i/o gpio /spi0sck/timer2/ppidata5 c pf11 /spi0_miso/pwm0_trip /ppi_d4/taclk2 i/o gpio /spi0 miso/pwm0 trip/ppi data 4/alt timer clk 2 c pf12 /spi0_mosi/pwm0_sync/ppi_d3 i/o gpio /spi0 mosi/pwm0 sync/ppi data 3 c pf13 /spi0_sel1 /tmr3/ppi_d2/spi0_ss i/o gpio /spi0 slave select 1/timer3/ppi data 2/spi0 slave select in c pf14 /spi0_sel2 /pwm0_ah/ppi_d1 i/o gpio /spi0 slave select 2/pwm0 ah/ppi data 1 c pf15 /spi0_sel3 /pwm0_al/ppi_d0 i/o gpio /spi0 slave select 3/pwm0 al/ppi data 0 c port g: gpio and multiplexed peripherals pg0 /spi1_sel3 /tmrclk/ppi_clk/ua1_rx/taci4 i/o gpio /spi1 slave select 3/timer clk/ppi clock/uart1 rx/alt capture in 4 c pg1 /spi1_sel2 /ppi_fs3/can_rx/taci5 i/o gpio /spi1 slave select 2/ppi fs3/can rx/alt capture in 5 c pg2 /spi1_sel1 /tmr4/can_tx/spi1_ss i/o gpio /spi1 slave select 1/timer4/can tx/spi1 slave select in c pg3 /hwait/spi1_sck/dt1sec/ua1_tx i/o gpio /hwait/spi1 sck/sport1 tx sec data/uart1 tx c pg4 /spi1_mosi/dr1sec/ pwm1_sync/taclk6 i/o gpio /spi1 mosi/sport1 sec rx data/pwm1 sync/alt timer clk 6 c pg5 /spi1_miso/tmr7/pwm1_trip i/o gpio /spi1miso/timer7/pwm1 trip c pg6 /acm_sgldiff/sd_d3/pwm1_ah i/o gpio /adccmsgl diff/sddata3/pwm1drive a hi c pg7 /acm_range/sd_d2/pwm1_al i/o gpio /adc cm range/sd data 2/pwm1 drive a lo c pg8 /dr1sec/sd_d1/pwm1_bh i/o gpio /sport1 sec rx data/sddata1/pwm1drive b hi c pg9 /dr1pri/sd_d0/pwm1_bl i/o gpio /sport1prirxdata/sddata0/pwm1drive b lo c pg10 /rfs1/sd_cmd/pwm1_ch/taci6 i/o gpio /sport1rxframesync/sdcmd/pwm1 drive c hi/altcapturein6 c pg11 /rsclk1/sd_clk/pwm1_cl/taclk7 i/o gpio /sport1rxserialclk/sdclk/pwm1drive c lo/alttimerclk7 c pg12 /ua0_rx/sd_d4/ppi_d15/taci2 i/o gpio /uart0rx/sddata4/ppidata15/altcapturein2 c pg13 /ua0_tx/sd_d5/ppi_d14/czm1 i/o gpio /uart0tx/sddata5/ppidata14/counter zero marker 1 c rev. a | page 22 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f pg14 /ua0_rts /sd_d6/tmr0/ppi_fs1/cud1 i/o gpio /uart0 rts/sd data 6/timer0/ppi fs1/count up dir 1 c pg15 /ua0_cts /sd_d7/tmr1/ppi_fs2/cdg1 i/o gpio /uart0 cts/sd data 7/timer1/ppi fs2/count down dir 1 c port h: gpio and multiplexed peripherals ph0 /acm_a2/dt1pri/spi0_sel3 /wakeup i/o gpio /adccma2/sport1txpridata/spi0slaveselect3 / wake-up input c ph1 /acm_a1/tfs1/spi1_sel3 /taclk3 i/o gpio /adccma1/sport1txframesync/spi1slaveselect3/alttimer clk3 c ph2 /acm_a0/tsclk1/spi1_sel2 /taci7 i/o gpio /adc cm a0/sport1 tx serial clk/spi1 slave select 2/alt capture in 7 c twi (2-wire interface) port scl i/o 5v twi serial clock (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) d sda i/o 5v twi serial data (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) d jtag port tck i jtag clk tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this signal should be pulled low if the jtag port is not used.) emu o emulation output c clock clkin i clk/crystal in xtal o crystal output extclk o clock output b mode controls reset ireset nmi i nonmaskable interrupt (this signal should be pulled high when not used.) bmode2C0 i boot mode strap 2-0 adsp-bf50x voltage regulation i/f ext_wake o wake up indication c pg i power good power supplies all supplies must be powered see processoroperating co nditions on page 25 . v ddext pi/opowersupply v ddint p internal power supply v ddflash p flash memory power supply gnd g ground for all supplies table 11. processorsignal de scriptions (continued) signal name type function driver type rev. a | page 23 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 12. adcsignal descriptions (adsp-bf506f processor only) signal name type function dgnd g digital ground. this is the ground reference point fo r all digital circuitry on th e internal adc. both dgnd pins should connect to the dgnd plane of a system . the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. ref select i internal/external reference selection. logic input. if this pin is tied to dgnd, the on-chip 2.5 v reference is used as the reference source for both adc a and adc b. in addition, pin d cap a and pin d cap b must be tied to decoupling capacitors. if the ref select pin is tied to a logic high, an external reference can be supplied to the internal adc through the d cap a and/or d cap b pins. av dd p analog supply voltage, 2.7 v to 5.25 v. this is th e only supply voltage for all analog circuitry on the internal adc. the av dd and dv dd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. this supply should be decoupled to agnd. d cap a, d cap b (v ref ) i decoupling capacitor pins. decoupling capacitors (470 nf recommended) are connected to these pins to decouple the reference buffer for each respective adc. provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. the range of the external reference is dependent on the analog input range selected. agnd g analog ground. ground reference point for all anal og circuitry on the internal adc. all analog input signals and any external reference signal should be referred to this agnd voltage. all three of these agnd pins should connect to the agnd plane of a system. the agnd and dgnd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. v a1 to v a6 i analog inputs of adc a. these may be programmed as six single-ended channels or three true differ- ential analog input channel pairs. see table 53 ( analog input type and channel selection ). v b1 to v b6 i analog inputs of adc b. these ma y be programmed as six single-end ed channels or three true differ- ential analog input channel pairs. see table 53 ( analog input type and channel selection ). range i analog input range selection. logic input. the pol arity on this pin determines the input range of the analog input channels. if this pin is tied to a logic low, the analog input range is 0 v to v ref . if this pin is tied to a logic high when cs goes low, the analog input range is 2 v ref . for details, see table 53 ( analog input type and channel selection ). sgl/diff i logic input. this pin selects whether the analog inp uts are configured as differential pairs or single ended. a logic low selects differential operation while a logic high selects single-ended operation. for details, see table 53 ( analog input type and channel selection ). a0 to a2 i multiplexer select. logic inputs. these inputs ar e used to select the pair of channels to be simultane- ously converted, such as channel 1 of both adc a and adc b, channel 2 of both adc a and adc b, and so on. the pair of channels selected may be two si ngle-ended channels or two differential pairs. the logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge of cs to correctly set up the multiplexer for that conversion. for further details, see table 53 ( analog input type and channel selection ). cs i chip select. active low logic input. this input provid es the dual function of initiating conversions on the internal adc and framing the serial data transfer. when connecting cs to a processor signal that is three-stated during reset and/or hibernate, adding a pull-up resistor may prove useful to avoid random adc operation. adsclk i serial clock. logic input. a serial clock input provides the adsclk for accessing the data from the internal adc. this clock is also used as the clock source for the conversion process. rev. a | page 24 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f d out a, d out b o serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the adsclk input and 14 adsclks are required to access the data. the data simultaneously appears on both pins from the simult aneous conversions of both adcs. the data stream consists of two leading zeros followed by the 12 bits of conversion data. the data is provided msb first. if cs is held low for 16 adsclk cycles rather than 14, then two trailing zeros will appear after the 12 bits of data. if cs is held low for a further 16 adsclk cycles on either d out a or d out b, the data from the other adc follows on the d out pin. this allows data from a simult aneous conversion on both adcs to be gathered in serial format on either d out a or d out b using only one serial port. for more information, see the adcserial interface section. v drive p logic power supply input. the voltage supplied at this pin determines at what voltage the digital i/o interface operates. this pin should be decoupled to dgnd. the voltage at this pin may be different than that at av dd and dv dd but should never exceed either by more than 0.3 v. dv dd p digital supply voltage, 2.7 v to 5.25 v. this is the supply voltage for all digital circuitry on the internal adc. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to dgnd. table 12. adcsignal descriptions (ads p-bf506f processor only) (continued) signal name type function rev. a | page 25 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processorspecifications specifications are subject to change without notice. processoroperating conditions table 13 shows settings for twi_dt in the nongpio_drive register. set this register prior to using the twi port. parameter conditions min nominal max unit v ddint internal supply voltage industrial models 1.14 1.47 v internal supply voltage commercial models 1.10 1.47 v internal supply voltage automotive models 1.33 1.47 v v ddext 1,2 1 must remain powered (even if the as sociated function is not used). 2 1.8 v and 2.5 v i/o are supported only on ADSP-BF504 nonautomotive models. all adsp-bf50x flash and automotive models support 3 .3 v i/o only. external supply voltage 1.8 v i/o, ADSP-BF504, nonautomotive and non flash models 1.7 1.8 1.9 v external supply voltage 2.5 v i/o, ADSP-BF504, nonautomotive and non flash models 2.25 2.5 2.75 v external supply voltage 3.3 v i/o, adsp-bf50x, all models 2.7 3.3 3.6 v v ddflash 1,3 3 for ADSP-BF504, v ddflash pins should be connected to gnd. flash memory supply voltage 1.7 1.8 2.0 v v ih high level input voltage 4, 5 4 bidirectional pins (pf15C0, pg15C0, ph2C 0) and input pins (tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the adsp-bf50x processors are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 5 parameter value applies to all input and bidirectional pins, except sda and scl. v ddext = 1.90 v 1.2 v high level input voltage 4, 5 v ddext = 2.75 v 1.7 v high level input voltage 4, 5 v ddext = 3.6 v 2.0 v v ihtwi high level input voltage 6 6 parameter applies to sda and scl. v ddext = 1.90 v/2.75 v/3.6 v 0.7 v bustwi 7, 8 v bustwi 7, 8 7 the v ihtwi min and max value vary with the selection in the twi_dt field of the nongpio_drive register. see v bustwi min and max values in table 13 . v v il low level input voltage 4, 5 v ddext = 1.7 v 0.6 v low level input voltage 4, 5 v ddext = 2.25 v 0.7 v low level input voltage 4, 5 v ddext = 3.0 v 0.8 v v iltwi low level input voltage 6 v ddext = minimum 0.3 v bustwi 8 8 sda and scl are pulled up to v bustwi . see table 13 . v t j junction temperature 88-lead lfcsp @ t ambient = C40c to +85c C40 +105 c junction temperature 88-lead lfcsp @ t ambient = 0c to +70c 0 +90 c junction temperature 120-lead lqfp @ t ambient = C40c to +85c C40 +105 c junction temperature 120-lead lqfp @ t ambient = 0c to +70c 0 +90 c junction temperature 88-lead lfcsp @ t ambient = C40c to +105c C40 +125 c table 13. twi_dt field selections and v ddext /v bustwi twi_dt v ddext nominal v bustwi minimum v bustwi nominal v bustwi maximum unit 000 (default) 3.3 2.97 3.3 3.63 v 001 1.8 1.7 1.8 1.98 v 010 2.5 2.97 3.3 3.63 v 011 1.8 2.97 3.3 3.63 v 100 3.3 4.5 5 5.5 v 101 1.8 2.25 2.5 2.75 v 110 2.5 2.25 2.5 2.75 v 111 (reserved) rev. a | page 26 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adsp-bf50x clock related operating conditions table 14 describes the core clock timing requirements for the adsp-bf50x processors. take ca re in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock (see table 16 ). table 15 describes phase- locked loop operating conditions. table 14. core clock (cclk) requirements adsp-bf50x processorsall speed grades parameter min v ddint nom v ddint max cclk frequency unit f cclk core clock frequency (all models) 1.33 v 1.400 v 400 mhz core clock frequency (industrial/commercial models) 1.16 v 1.225 v 300 mhz core clock frequency (industrial models only) 1.14 v 1.200 v 200 mhz core clock frequency (commercial models only) 1.10 v 1.150 v 200 mhz table 15. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency (commercial/industrial models) 72 instruction rate 1 mhz voltage controlled oscillator (vco) frequency (automotive models) 84 instruction rate 1 mhz 1 for more information, see ordering guide on page 80. table 16. maximum sclk conditions for adsp-bf50x processors parameter v ddext = 1.8 v/2.5 v/3.3 v nominal unit f sclk clkout/sclk frequency (v ddint 1.16 v) 100 mhz clkout/sclk frequency (v ddint < 1.16 v) 80 mhz rev. a | page 27 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processorelectrical characteristics parameter test conditions min typical max unit v oh high level output voltage v ddext = 1.7 v, i oh = C0.5 ma 1.35 v high level output voltage v ddext = 2.25 v, i oh = C0.5 ma 2.0 v high level output voltage v ddext = 3.0 v, i oh = C0.5 ma 2.4 v v ol low level output voltage v ddext = 1.7 v/2.25 v/3.0 v, i ol = 2.0 ma 0.4 v i ih high level input current 1 v ddext =3.6 v, v in = 3.6 v 10.0 a i il low level input current 1 v ddext =3.6 v, v in = 0 v 10.0 a i ihp high level input current jtag 2 v ddext = 3.6 v, v in = 3.6 v 75.0 a i ozh three-state leakage current 3 v ddext = 3.6 v, v in = 3.6 v 10.0 a i ozhtwi three-state leakage current 4 v ddext =3.0 v, v in = 5.5 v 10.0 a i ozl three-state leakage current 3 v ddext = 3.6 v, v in = 0 v 10.0 a c in input capacitance 5,6 f in = 1 mhz, t ambient = 25c, v in =2.5v 58 pf c intwi input capacitance 4,6 f in = 1 mhz, t ambient = 25c, v in =2.5v 10 pf i dddeepsleep 7 v ddint current in deep sleep mode v ddint = 1.2 v, f cclk = 0 mhz, f sclk =0mhz, t j = 25c, asf = 0.00 1.85 ma i ddsleep v ddint current in sleep mode v ddint = 1.2 v, f sclk = 25 mhz, t j = 25c 2.1 ma i dd-idle v ddint current in idle v ddint = 1.2 v, f cclk = 50 mhz, t j = 25c, asf = 0.42 18 ma i dd-typ v ddint current v ddint = 1.40 v, f cclk = 400 mhz, t j = 25c, asf = 1.00 104 ma v ddint current v ddint = 1.225 v, f cclk = 300 mhz, t j = 25c, asf = 1.00 69 ma v ddint current v ddint = 1.2 v, f cclk = 200 mhz, t j = 25c, asf = 1.00 51 ma i ddhibernate 8 hibernate state current v ddext =3.30v, v ddflash =1.8 v, t j = 25c, clkin = 0 mhz (v ddint = 0 v) 40 a i ddsleep 9 v ddinit current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz table 18 + (.16 v ddint f sclk ) ma 10 i dddeepsleep 9 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 18 ma i ddint 9 v ddint current f cclk > 0 mhz, f sclk 0 mhz table 18 + ( table 19 asf) + (.16 v ddint f sclk ) ma i ddflash1 flash memory supply current 1 asynchronous read (5 mhz norclk 11 ) 10 20 ma flash memory supply current 1 synchronous read (50 mhz norclk 11 ) 4 word 18 20 ma 8 word 20 22 ma 16 word 25 27 ma continuous 28 30 ma rev. a | page 28 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f i ddflash2 flash memory supply current 2 reset/powerdown 15 50 a i ddflash3 flash memory supply current 3 standby 15 50 a i ddflash4 flash memory supply current 4 automatic standby 15 50 a i ddflash5 flash memory supply current 5 program 15 40 ma flash memory supply current 5 erase 15 40 ma i ddflash6 flash memory supply current 6 dual operations program/erase in one bank, asynchronous read in another bank 25 60 ma program/erase in one bank, synchronous read in another bank 43 70 ma i ddflash7 flash memory supply current 7 program/erase suspended (standby) 15 50 a 1 applies to input pins. 2 applies to jtag input pins (tck, tdi, tms, trst) . 3 applies to three-statable pins. 4 applies to bidirectional pins scl and sda. 5 applies to all signal pins, except scl and sda. 6 guaranteed, but not tested. 7 see the adsp-bf50x blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 8 applies to v ddext supply only. clock inputs are tied high or low. 9 guaranteed maximum specifications. 10 unit for v ddint is v (volts). unit for f sclk is mhz. example: 1.4 v, 75 mhz would be 0.16 x 1.4 x 75 = 16.8 ma adder. 11 see the adsp-bf50x blackfin processor hardware reference manual for definition of norclk. parameter test conditions min typical max unit rev. a | page 29 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. processorelectrical characteristics on page 27 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipation as a function of voltage (v ddint ) and temperature (see table 18 ), and i ddint specifies the total power specific ation for the listed test condi- tions, including the dynamic comp onent as a function of voltage (v ddint ) and frequency ( table 19 ). there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf) which represents application code runn ing on the processor core and l1 memories ( table 17 ). the asf is combined with the cclk frequency and v ddint dependent data in table 19 to calculate this part. the second part is due to transistor switch ing in the system clock (sclk) domain, which is included in the i ddint specification equation. table 17. activity scaling factors (asf) 1 1 see estimating power for a sdp-bf534/bf536/bf537 blackfin processors (ee-297) . the power vector information al so applies to the adsp-bf50x processors. i ddint power vector activity scaling factor (asf) i dd-peak 1.27 i dd-high 1.24 i dd-typ 1.00 i dd-app 0.85 i dd-nop 0.71 i dd-idle 0.42 table 18. adsp-bf50x static current i dd-deepsleep (ma) t j (c) 1 voltage (v ddint ) 1 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v C40 1.0 1.0 1.1 1.1 1.2 1.3 1.7 1.9 C20 1.1 1.2 1.3 1.4 1.6 1.7 1.9 2.0 0 1.3 1.4 1.6 1.8 2.0 2.2 2.3 2.5 25 1.9 2.1 2.3 2.5 2.8 3.1 3.3 3.7 40 2.6 2.8 3.0 3.3 3.7 4.0 4.4 4.9 55 3.5 3.8 4.3 4.6 5.0 5.5 6.1 6.7 70 5.0 5.4 6.0 6.4 7.0 7.7 8.4 9.2 85 7.1 7.7 8.3 9.1 9.9 10.8 11.8 12.8 100 10.0 10.8 11.7 12.7 13.7 15.0 16.1 17.5 105 11.1 12.1 13.1 14.2 15.3 16.6 18.0 19.4 1 valid temperature and voltage ranges are model-specific. see processoroperating conditions on page 25 . table 19. adsp-bf50x dynamic current in cclk domain (ma, with asf = 1.0) 1 f cclk (mhz) 2 voltage (v ddint ) 2 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v 400 n/a n/a n/a n/a 84.46 88.30 92.39 96.35 100.49 350 n/a n/a n/a n/a 74.30 77.93 81.39 84.94 88.61 300 n/a n/a 58.58 61.46 64.49 67.59 70.71 73.76 77.04 250 43.76 46.22 48.64 51.09 53.61 56.19 58.93 61.56 64.22 200 35.26 37.37 39.29 41.33 43.40 45.54 47.79 49.88 52.18 150 26.71 28.38 29.87 31.46 33.09 34.83 36.56 38.22 39.95 100 18.04 19.20 20.25 21.46 22.61 23.83 25.13 26.39 27.72 1 the values are not guaranteed as standalone maximum specifications. they must be combined with static current per the equations of processorelectrical characteristics on page 27 . 2 valid frequency and voltage ra nges are model-specific. see processoroperating conditions on page 25 and adsp-bf50x clock related oper ating conditions on page 26 . rev. a | page 30 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processorabsolute maximum ratings stresses greater than those listed in table 20 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 22 specifies the maximum total source/sink (i oh /i ol ) cur- rent for a group of pins. permanent damage can occur if this value is exceeded. to understand this specification, if pins pg5, pg6, pg7, pg8, and pg9 from group 5 in the total current pin groups table, each were sourcing or sinking 2 ma each, the total current for those pins would be 10 ma. this would allow up to 66 ma total that could be sourced or sunk by the remain- ing pins in the group without dama ging the device. for a list of all groups and their pins, see the total current pin groups table. note that the v ol and v ol specifications have separate per-pin maximum current requirements, see the processor electrical characteristics table. table 20. absolute maximum ratings parameter rating internal supply voltage (v ddint )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 21 . 2 applies only when v ddext is within specif ications. when v ddext is outside speci- fications, the range is v ddext 0.2 v. C0.5 v to +3.6 v input voltage 1, 2, 3 3 applies to pins scl and sda. C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext +0.5 v i oh /i ol current per pin group 4 4 for more information, se e description preceding table 22 . 76 ma (max) storage temperature range C65 c to +150 c junction temperature while biased (non-automotive models) +110 c junction temperature while biased (automotive models) +125 c table 21. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with th e exception of clkin, xtal, ext_wake. v in min (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less th an or equal to the corresponding duty cycle. v in max (v) 2 maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. the is equivalent to the meas ured duration of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.50 +3.80 100% C0.70 +4.00 40% C0.80 +4.10 25% C0.90 +4.20 15% C1.00 +4.30 10% table 22. total current pin groups group pins in group 1pf10, pf11 2 pf12, pf13, pf14, pf15 3pg0 4 pg1, pg2, pg3, pg4 5 pg5, pg6, pg7, pg8, pg9, pg10, pg11 6 pg12, pg13, pg14, pg15, sda, scl 7emu , ext_wake, pg 8 pf0, pf1, ph0, ph1, ph2 9extclk 10 pf2, pf3, pf4, pf5, pf6, pf7, pf8, pf9 rev. a | page 31 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f esd sensitivity package information the information presented in figure 9 and table 23 provides details about the package br anding for the adsp-bf50x processors. esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. figure 9. product information on package table 23. package brand information 1 1 non automotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description adsp-bf50x product name 2 2 see product names in the ordering guide on page 80 . t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliance designator yyww date code vvvvvv.x n.n tppzccc adsp-bf50x a #yyww country_of_origin b rev. a | page 32 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processortiming specifications specifications subject to change without notice. clock and reset timing table 24 and figure 10 describe clock and reset operations. per the cclk and sclk timing specifications in table 14 to table 16 , combinations of clkin and clock multipliers must not select core/peripheral clocks in excess of the processors speed grade. table 25 and figure 11 describe clock out timing. table 24. clock and reset timing parameter min max unit timing requirement s f ckin clkin frequency 1, 2, 3, 4 (commercial/industrial models) 12 50 mhz clkin frequency 1, 2, 3, 4 (automotive models) 14 50 mhz t ckinl clkin low pulse 1 10 ns t ckinh clkin high pulse 1 10 ns t wrst reset asserted pulse width low 5 11 t ckin ns switching characteristic t bufdlay clkin to clkbuf 6 delay 11 ns 1 applies to pll bypass mode and pll non bypass mode. 2 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 14 on page 26 through table 16 on page 26 . 3 the t ckin period (see figure 10 ) equals 1/f ckin . 4 if the df bit in the pll_ctl register is set, the minimum f ckin specification is 24 mhz for co mmercial/industrial models and 28 mhz for automotive models. 5 applies after power-up se quence is complete. see table 26 and figure 12 for power-up reset timing. 6 the ADSP-BF504/ADSP-BF504f/ adsp-bf506f processor does not have a dedicated cl kbuf pin. rather, the extclk pin may be programmed to serve as clkbuf or clkout. this parameter applies when extclk is programmed to output clkbuf. figure 10. clock and reset timing clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset clkbuf rev. a | page 33 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 25. clock out timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit switching characteristics t sclk clkout 1 period 2,3 10 10 ns t sclkh clkout 1 width high 44ns t sclkl clkout 1 width low 4 4 ns 1 the ADSP-BF504/ADSP-BF504f/adsp-bf 506f processor does not have a dedicated clko ut pin. rather, the extcl k pin may be programmed to serve as clkbuf or clkout. this parameter applies when extclk is programmed to output clkout. 2 the t sclk value is the inverse of the f sclk specification. reduced supply voltages affect the best-case value of 10 ns listed here. 3 the t sclk value does not account for the effects of jitter. figure 11. clock out timing t sclkl t sclkh t sclk clkout table 26. power-up reset timing parameter min max unit timing requirement s t rst _ in _ pwr reset deasserted after the v ddint , v ddext , v ddflash , and clkin pins are stable and within specification 3500 t ckin ns in figure 12 , v dd_supplies is v ddint , v ddext , and v ddflash . figure 12. power -up reset timing reset t rst_in_pwr clkin v dd_supplies rev. a | page 34 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f parallel peripheral interface timing table 27 and figure 14 on page 34 , figure 20 on page 39 , and figure 22 on page 40 describe parallel peripheral interface operations. table 27. parallel peripheral interface timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t pclkw ppi_clk width 1 t sclk C1.5 t sclk C1.5 ns t pclk ppi_clk period 1 2 t sclk C1.5 2 t sclk C1.5 ns timing requirementsgp input and frame capture modes t psud external frame sync startup delay 2 4 t pclk 4 t pclk ns t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 6.7 ns t hfspe external frame sync hold after ppi_clk 1.5 1.5 ns t sdrpe receive data setup before ppi_clk 4.1 3.5 ns t hdrpe receive data hold after ppi_clk 2 1.6 ns switching characteristicsgp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 8.7 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 8.7 8.0 ns t hdtpe transmit data hold after ppi_clk 2.3 1.9 ns 1 ppi_clk frequency cannot exceed f sclk /2 2 the ppi port is fully enabled 4 ppi clock cy cles after the pab write to the ppi port en able bit. only after the ppi port is ful ly enabled are external frame syncs and data words guaranteed to be received co rrectly by the ppi peripheral. figure 13. ppi with external frame sync timing figure 14. ppi gp rx mode with external frame sync timing ppi_clk ppi_fs1/2 t psud t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw rev. a | page 35 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 15. ppi gp tx mode with external frame sync timing figure 16. ppi gp rx mode with internal frame sync timing figure 17. ppi gp tx mode wi th internal frame sync timing t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven rev. a | page 36 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f rsi controller timing table 28 and figure 18 describe rsi controller timing. table 29 and figure 19 describe rsi controller (high speed) timing. table 28. rsi controller timing parameter min max unit timing requirements t isu input setup time 5.75 ns t ih input hold time 2 ns switching characteristics f pp 1 clock frequency data transfer mode 0 25 mhz f od clock frequency identification mode 100 2 400 khz t wl clock low time 10 ns t wh clock high time 10 ns t tlh clock rise time 10 ns t thl clock fall time 10 ns t odly output delay time during data transfer mode 14 ns t odly output delay time during identification mode 50 ns 1 t pp = 1/f pp 2 specification can be 0 kh z, which means to stop the clock. the given minimum frequency range is for ca ses where a continuous cl ock is required. figure 18. rsi controller timing sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly v oh (min) v ol (max) rev. a | page 37 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 29. rsi controller timing (high speed mode) parameter min max unit timing requirements t isu input setup time 5.75 ns t ih input hold time 2 ns switching characteristics f pp 1 clock frequency data transfer mode 0 50 mhz t wl clock low time 7 ns t wh clock high time 7 ns t tlh clock rise time 3ns t thl clock fall time 3ns t odly output delay time during data transfer mode 2.5 ns t oh output hold time 2.5 ns 1 t pp = 1/f pp figure 19. rsi controller timing (high-speed mode) sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly t oh v oh (min) v ol (max) rev. a | page 38 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f serial ports table 30 through table 33 on page 40 and figure 20 on page 39 through figure 22 on page 40 describe serial port operations. table 30. serial portsexternal clock parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclkx 1 3.0 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclkx 1 3.0 3.0 ns t sdre receive data setup before rsclkx 1,2 3.0 3.0 ns t hdre receive data hold after rsclkx 1,2 3.5 3.0 ns t sclkew tsclkx/rsclkx width 4.5 4.5 ns t sclke tsclkx/rsclkx period 2 t sclk 2 t sclk ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 10.0 10.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 0.0 0.0 ns t ddte transmit data delay after tsclkx 3 11.0 10.0 ns t hdte transmit data hold after tsclkx 3 0.0 0.0 ns 1 referenced to sample edge. 2 when sport is used in conjunc tion with the acm, refer to the timing requirements in table 41 ( acm timing ). 3 referenced to drive edge. table 31. serial portsinternal clock parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.0 9.6 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 C1.5 C1.5 ns t sdri receive data setup before rsclkx 1,2 11.5 10.0 ns t hdri receive data hold after rsclkx 1,2 C1.5 C1.5 ns switching characteristics t sclkiw tsclkx/rsclkx width 7.0 8.0 ns t dfsi tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 4.0 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 C2.0 C1.0 ns t ddti transmit data delay after tsclkx 3 4.0 3.0 ns t hdti transmit data hold after tsclkx 3 C1.8 C1.5 ns 1 referenced to sample edge. 2 when sport is used in conjunc tion with the acm, refer to the timing requirements in table 41 ( acm timing ). 3 referenced to drive edge. rev. a | page 39 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 20. serial ports table 32. serial portsenable and three-state parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit switching characteristics t dtene data enable delay from external tsclkx 1 0.0 0.0 ns t ddtte data disable delay from external tsclkx 1 t sclk +1 t sclk +1 ns t dteni data enable delay from internal tsclkx 1 C2.0 C2.0 ns t ddtti data disable delay from internal tsclkx 1 t sclk +1 t sclk +1 ns 1 referenced to drive edge. figure 21. serial ports enable and three-state t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx dtx drive edge t ddtte/i t dtene/i drive edge rev. a | page 40 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 33. serial ports external late frame sync parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx in multi-channel mode with mfd = 0 1, 2 12.0 10.0 ns t dtenlfse data enable from external rfsx in multi-channel mode with mfd = 0 1, 2 0.0 0.0 ns 1 when in multi-channel mode, tfsx enable and tfsx valid follow t dtenlfse and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2 then t ddtte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfse apply. figure 22. serial ports external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse rev. a | page 41 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f serial peripheral interface (spi) portmaster timing table 34 and figure 23 describe spi port master operations. table 34. serial peripheral interface (spi) portmaster timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 11.6 9.6 ns t hspidm sck sampling edge to data input invalid C1.5 C1.5 ns switching characteristics t sdscim spiselx low to first sck edge 2 t sclk C1.5 2 t sclk C1.5 ns t spichm serial clock high period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclm serial clock low period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 4 t sclk C1.5 ns t hdsm last sck edge to spiselx high 2 t sclk C2.0 2 t sclk C1.5 ns t spitdm sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 0606ns t hdspidm sck edge to data out invalid (data out hold) C1.0 C1.0 ns figure 23. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm rev. a | page 42 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f serial peripheral interface (spi) portslave timing table 35 and figure 24 describe spi port slave operations. table 35. serial peripheral interface (spi) portslave timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk 4 t sclk ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk C1.5 2 t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 1.6 ns t hspid sck sampling edge to data input invalid 2.0 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 12.0 0 10.3 ns t dsdhi spiss deassertion to data high impedance 0 11.0 0 9.0 ns t ddspid sck edge to data out valid (data out delay) 10 10 ns t hdspid sck edge to data out invalid (data out hold) 0 0 ns figure 24. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid rev. a | page 43 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-bf50x hardware reference manual . general-purpose port timing table 36 and figure 25 describe general-purpose port operations. table 36. general-purpose port timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirement t wfi general-purpose port pin input pulse width t sclk + 1 t sclk + 1 ns switching characteristic t gpod general-purpose port pin output delay from clkout high 0 11.0 0 8.9 ns figure 25. general-purpose port timing clkout gpio output gpio input t wfi t gpod rev. a | page 44 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f timer cycle timing table 37 and figure 26 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 37. timer cycle timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t wl timer pulse width input low (measured in sclk cycles) 1 1 t sclk 1 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 1 t sclk 1 t sclk ns t tis timer input setup time before clkout low 2 10 8 ns t tih timer input hold time after clkout low 2 C2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) 1 t sclk C 2.0 (2 32 C1) t sclk 1 t sclk C 1.5 (2 32 C1) t sclk ns t tod timer output update delay after clkout high 6 6 ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock mode s. they also apply to the pg0 or ppi_cl k signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 26. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto rev. a | page 45 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f timer clock timing table 38 and figure 27 describe timer clock timing. up/down counter/rotary encoder timing table 38. timer clock timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit switching characteristic t todp timer output update delay after ppi_clk high 12.0 12.0 ns figure 27. timer clock timing table 39. up/down counter/rotary encoder timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t wcount up/down counter/rotary encoder input pulse width t sclk + 1 t sclk + 1 ns t cis counter input setup time before clkout high 1 1 either a valid setup and hold time or a valid pulse width is su fficient. there is no need to resynchronize counter inputs. 9.0 7.0 ns t cih counter input hold time after clkout high 1 00ns figure 28. up/down counter/rotary encoder timing ppi_clk tmrx output t todp clkout cud/cdg/czm t cis t cih t wcount rev. a | page 46 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f pulse width modulator (pwm) timing table 40 and figure 29 describe pwm operations. table 40. pwm timing parameter min max unit timing requirements t es external sync pulse width 2 t sclk + 1 ns switching characteristics t dodis output 1 inactive (off) after trip input 12 ns t doe output 1 delay after external sync 2 2 t sclk 5 t sclk + 13 ns t od output 1 delay after falling edge of clkout 5 ns 1 pwm outputs are: pwmx_ah, pwmx_al, pwmx_bh, pwmx_bl, pwmx_ch, and pwmx_cl. 2 when the external sync signal is synchronou s to the peripheral clock, it takes fewer clock cycles for the output to appear comp ared to when the external sync signal is asynchronous to the peripheral cloc k. for more information, see the adsp-bf50x blackfin proc essor hardware reference . figure 29. pwm timing pwmx_trip pwmx_sync (as input) t es t doe output t od t dodis clkout rev. a | page 47 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adc controller module (acm) timing table 41 and figure 30 describe acm operations. note that the acm clock (aclk) frequency in mhz is set by the following equation (in wh ich acmckdiv ranges from 0 to 255). f aclk f sclk 2acmckdiv () 2 + -------------------------------------------------------- = t aclk 1 f aclk -------------- = table 41. acm timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max units timing requirements t sdr sport drxpri/drxsec setup before aclk 8.0 7.0 ns t hdr sport drxpri/drxsec hold after aclk 0 0 ns switching characteristics t do acm controls (acm_a[2:0], acm_range, acm_sgldiff) delay after falling edge of clkout 8.4 8.4 ns t daclk aclk delay after falling edge of clkout 4.5 4.5 ns t dcs cs active edge delay after falling edge of clkout 5.6 5.3 ns t dcsaclk the delay between the active edge of cs and the first edge of aclk t aclk C 5 t aclk C 5 ns figure 30. acm timing cs t dcsaclk aclk acm controls drxpri/ drxsec clkout t dcs t daclk t do t sdr t hdr rev. a | page 48 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f jtag test and emulation port timing table 42 and figure 31 describe jtag port operations. table 42. jtag port timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t tck tck period 20 20 ns t stap tdi, tms setup before tck high 4 4 ns t htap tdi, tms hold after tck high 4 4 ns t ssys system inputs setup before tck high 1 44ns t stwi twi system inputs setup before tck high 2 n/a 5 ns t hsys system inputs hold after tck high 1 55ns t trstw trst pulse width 3 (measured in tck cycles) 4 4 tck switching characteristics t dtdo tdo delay from tck low 10 10 ns t dsys system outputs delay after tck low 4 12 12 ns 1 applies to system inputs = pf15C0, pg15C0, ph2C0, nmi , bmode3C0, reset . 2 applies to twi system inputs = scl, sda. for sda and sc l system inputs, the system design must comply with v ddext and vbustwi voltages specified for the default twi_dt (000) setting in table 13 . 3 50 mhz maximum 4 system outputs = extclk, scl, sda, pf15C0, pg15C0, ph2C0. figure 31. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys rev. a | page 49 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processoroutput drive currents figure 32 through figure 40 show typical current-voltage char- acteristics for the output drivers of the adsp-bf50xf processors. the curves represent the current drive capability of the output drivers. see table 11 on page 21 for information about which driver type corresponds to a particular ball. figure 32. driver type b current (3.3 v v ddext ) figure 33. driver type b current (2.5 v v ddext ) figure 34. driver type b current (1.8 v v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 240 120 80 C240 C120 C40 v ol v oh v ddext = 3.6v @ C 55 c v ddext = 3.3v @ 25 c C80 C200 40 160 v ddext = 3.0v @ 125 c C160 200 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 160 120 40 C160 C40 v ol v oh v ddext = 2.75v @ C 55 c v ddext = 2.5v @ 25 c 80 C80 v ddext = 2.25v @ 125 c C120 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 80 60 40 C60 C20 v ol v oh v ddext = 1.9v @ C 55 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 155 c C80 figure 35. driver type c current (3.3 v v ddext ) figure 36. drive type c current (2.5 v v ddext ) figure 37. driver type c current (1.8 v v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 60 40 C100 C60 C20 v ol v oh v ddext = 3.6v @ C 55 c v ddext = 3.3v @ 25 c C40 C80 20 80 v ddext = 3.0v @ 125 c 120 C120 2.5 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 80 40 20 C80 C20 v ol v oh v ddext = 2.75v @ C 55 c v ddext = 2.5v @ 25 c C40 v ddext = 2.25v @ 125 c C60 60 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 50 40 30 C50 C40 C10 v ol v oh v ddext = 1.9v @ C 55 c v ddext = 1.8v @ 25 c C20 10 v ddext = 1.7v @ 125 c 20 C30 rev. a | page 50 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processortest conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 41 shows the measurement point fo r ac measurements (except output enable/disable). the measurement point v meas is v ddext /2 for v ddext (nominal) = 1.8 v/2.5 v/3.3 v. output enable time measurement output pins are considered to be enabled when th ey have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 42 . the time t ena _ measured is the interval, from when the reference sig- nal switches, to when the output voltage reaches v trip (high) or v trip (low). for v ddext (nominal) = 1.8 v, v trip (high) is 1.05 v, and v trip (low) is 0.75 v. for v ddext (nominal) = 2.5 v, v trip (high) is 1.5 v and v trip (low) is 1.0 v. for v ddext (nominal) = 3.3 v, v trip (high) is 1.9 v, and v trip (low) is 1.4 v. time t trip is the interval from when the outp ut starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as shown in the equation: if multiple pins are enabled, th e measurement value is that of the first pin to start driving. figure 38. driver type d current (3.3 v v ddext ) figure 39. driver type d current (2.5 v v ddext ) figure 40. driver type d current (1.8 v v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 C40 C10 v ol v ddext = 3.6v @ C 55 c v ddext = 3.3v @ 25 c C20 C30 v ddext = 3.0v @ 125 c C50 C60 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 C35 C25 C10 v ol v ddext = 2.75v @ C 55 c v ddext = 2.5v @ 25 c C15 v ddext = 2.25v @ 125 c C20 C5 C30 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2 0 C16 C12 v ol v ddext = 1.9v @ C 55 c v ddext = 1.8v @ 25 c C14 v ddext = 1.7v @ 125 c C2 C4 C8 C6 C10 figure 41. voltage reference levels for ac measurements (except output enale/disale) figure 42. output enale/disale input or output v meas v meas reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low) t ena t ena_measured t trip ? = rev. a | page 51 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f output disable time measurement output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis _ measured and t decay as shown on the left side of figure 42 . the time for the voltage on the bus to decay by v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with v equal to 0.25 v for v ddext (nominal) = 2.5 v/3.3 v and 0.15 v for v ddext (nominal) = 1.8 v. the time t dis _ measured is the interval from when the reference sig- nal switches, to when the output voltage decays v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leak- age or three-state current (per da ta line). the hold time will be t decay plus the various output disa ble times as specified in the processortiming specifications on page 32 . capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all pins (see figure 43 ). v load is equal to (v ddext ) /2. the graphs of figure 44 through figure 49 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 43. equivalent device loading for ac measurements (includes all fixtures) t dis t dis_measured t decay ? = t decay c l v () i l ? = t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 figure 44. driver type b typical rise and fall times (10%?90%) vs. load capacitance (1.8 v v ddext ) figure 45. driver type b typical rise and fall times (10%?90%) vs. load capacitance (2.5 v v ddext ) figure 46. driver type b typical rise and fall times (10%?90%) vs. load capacitance (3.3 v v ddext ) 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 9 7 0 1 3 6 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 2 5 8 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 7 6 0 1 2 5 200 t rise t fall 3 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 3 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 6 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c rev. a | page 52 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f processorenvironmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c). t case = case temperature (c) measured by customer at top cen- ter of package. jt = from table 43 and table 44 . p d = power dissipation (see total power dissipation on page 29 for the method to calculate p d ). values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where t a = ambient temperature (c) values of jc are provided for packag e comparison and printed circuit board design considerations when an external heat sink is required. values of jb are provided for package comparison and printed circuit board design considerations. in table 43 and table 44 , airflow measurements comply with jedec standards jesd51-2 and je sd51-6, and th e junction-to- board measurement complies wi th jesd51-8. the junction-to- case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. figure 47. driver type c typical rise and fall times (10%C90%) vs. load capacitance (1.8 v v ddext ) figure 48. driver type c typical rise and fall times (10%C90%) vs. load capacitance (2.5 v v ddext ) figure 49. driver type c typical rise and fall times (10%C90%) vs. load capacitance (3.3 v v ddext ) 15 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 25 20 0 5 10 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 8 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 16 12 0 2 4 10 200 t rise t fall 6 14 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 6 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 14 12 0 2 4 8 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 10 table 43. thermal characteristics (88-lead lfcsp) parameter condition typical unit ja 0 linear m/s air flow 26.2 c/w jma 1 linear m/s air flow 23.7 c/w jma 2 linear m/s air flow 22.9 c/w jb 16.0 c/w jc 9.8 c/w jt 0 linear m/s air flow 0.21 c/w jt 1 linear m/s air flow 0.36 c/w jt 2 linear m/s air flow 0.43 c/w table 44. thermal characteristics (120-lead lqfp) parameter condition typical unit ja 0 linear m/s air flow 26.9 c/w jma 1 linear m/s air flow 24.2 c/w jma 2 linear m/s air flow 23.3 c/w jb 16.4 c/w jc 12.7 c/w jt 0 linear m/s air flow 0.50 c/w jt 1 linear m/s air flow 0.77 c/w jt 2 linear m/s air flow 1.02 c/w t j t case jt p d () + = t j t a ja p d () + = rev. a | page 53 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f flashspecifications specifications subject to change without notice. flashprogram and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in table 45 . exact erase times may change depending on the memory array condition. the best case is when all the bits in the block or bank are at 0 (pre programmed). the worst case is when all the bits in the block or bank are at 1 (not pre programmed). usually, the system overhead is negligible with respect to the erase time. flashabsolute maximum ratings table 46 shows the adc absolute maximum ratings. table 45. program/erase ti mes and endurance cycles parameter condition typical typical after 100k write/erase cycles max unit erase parameter block (4k word) 1 0.31 2.5s erase main block (32k word)preprogrammed 0.8 3 4 s erase main block (32k word)not preprogrammed 1 4 s program 2 word 12 12 100 s program 2 parameter block (4k word) 40 ms program 2 main block (32k word) 300 ms suspend latency program 5 10 s suspend latency erase 5 20 s program/erase cycles (per block) main blocks 100,000 cycles program/erase cycles (per block) parameter blocks 100,000 cycles 1 the difference between pre programmed and not pr e programmed is not s ignificant (< 30 ms). 2 values are liable to change with the external system-level over head (command sequence and stat us register polling execution). table 46. flash absolute maximum ratings parameter rating junction temperature while biased see table 20 on page 30 storage temperature range see table 20 on page 30 flash memory supply voltage (v ddflash ) C0.2 v to +2.45 v rev. a | page 54 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adcspecifications specifications are subject to change without notice. adcoperating conditions parameter conditions min nominal max unit v dd 1 (av dd , dv dd , v drive ) 1 throughout the adc sections of this data sheet, v dd refers to both av dd and dv dd . f adsclk = 24 mhz, f s up to 1.5 msps, internal or external reference = 2.5 v 1% unless otherwise noted 2.7 3.6 v f adsclk = 25 mhz, f s up to 1.56 msps, internal or external reference = 2.5 v 1% unless otherwise noted 3.0 3.6 v f adsclk = 32 mhz, f s up to 2.0 msps, internal or external reference = 2.5 v 1% unless otherwise noted 4.75 (av dd , dv dd ) 2.7 (v drive ) 5.25 (av dd , dv dd ) 5.25 (v drive ) v v t j junction temperature 120-lead lqfp @ t ambient = C40c to +85c C40 +105 c table 47. operating conditions (analog, voltage reference, and logic i/o) parameter specification unit test conditions/comments analog input 1 single-ended input range 0 v to v ref v range= low 0 v to 2 v ref vrange = high pseudo differential input range: v in+ C v inC 2 0 v to v ref v range = low 2 v ref vrange = high fully differential input range: v in+ and v inC v cm v ref /2 v v cm = common-mode voltage 3 = v ref /2, range = low v cm v ref vv cm = v ref , range = high dc leakage current 1 a max v a1 to v a6 , v b1 to v b6 input capacitance 4 45 pf typ when in track 10 pf typ when in hold internal voltage reference (output) 5 reference output voltage 2.5 0.4% v @ 25c, av dd = 2.7 v to 5.25 v long-term stability 4 150 ppm typ for 1000 hours output voltage thermal hysteresis 6 50 ppm typ d cap a, d cap b output impedance 4 10 typ reference temperature coefficient 4 60 max, 20 typ ppm/c v ref noise 4 20 v rms typ external voltage reference (input) 5 reference input voltage range 7 0.1 to av dd v see adctypical performance characteristics dc leakage current 7 2 a max input capacitance 4 25 pf typ digital logic inputs input high voltage, v inh 2.8 v min input low voltage, v inl 0.4 v max input current, i in 15 na typ v in = 0 v or v drive input capacitance, c in 4 5 pf typ rev. a | page 55 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f digital logic outputs output high voltage, v oh v drive C 0.2 v min no dc load (i oh = 0 ma) output low voltage, v ol 0.4 v max no dc load (i ol = 0 ma) floating state leakage current 1 a max v in = 0 v or v drive floating state output capacitance 4 7 pf typ output coding 8 straight (natural) binary twos complement 1 v inC or v in+ must remain within gnd/v dd . 2 v inC = 0 v for specified performance. for full input range on v inC pin, see figure 74 and figure 75 . 3 for full common-mode range, see figure 70 and figure 71 . 4 sample tested during initial release to ensure compliance. 5 relates to pin d cap a or pin d cap b (v ref ). 6 see adcterminology on page 60 . 7 external voltage reference applied to pins d cap a, pin d cap b (v ref ) 8 see table 52 and table 53 . table 48. operating conditions (adc performance/accuracy) parameter specification unit test conditions/comments dynamic performance signal-to-noise ratio (snr) 71 db min f in = 14 khz sine wave; differential mode 69 db min f in = 14 khz sine wave; single-ended and pseudo differential modes signal-to-(noise + distortion) ratio (sinad) 1 70 db min f in = 14 khz sine wave; differential mode 68 db min f in = 14 khz sine wave; single-ended and pseudo differential modes total harmonic distortion (thd) 1 C77 db max f in = 14 khz sine wave; differential mode C73 db max f in = 14 khz sine wave; single-ended and pseudo differential modes spurious-free dynamic range (sfdr) 1 C75 db max f in = 50 khz sine wave intermodulation distortion (imd) 1,2 f a = 30 khz, fb = 50 khz second-order terms C88 db typ third-order terms C88 db typ channel-to-channel isolation C88 db typ sample and hold aperture delay 2 11 ns max aperture jitter 2 50 ps typ aperture delay matching 2 200 ps max full power bandwidth 33/26 mhz typ @ 3 db, av dd , dv dd = 5 v/av dd , dv dd = 3 v 3.5/3 mhz typ @ 0.1 db, av dd , dv dd = 5 v/av dd , dv dd = 3 v table 47. operating conditions (analog, voltage reference, and logic i/o) (continued) parameter specification unit test conditions/comments rev. a | page 56 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f dc accuracy resolution 12 bits integral nonlinearity (inl) 1 1 lsb max 0.7 lsb typ; differential mode 1.5 lsb max 0.9 lsb typ; single-ended and pseudo differential modes differential nonlinearity (dnl) 1, 3 0.99 lsb max differential mode C0.99/+1.5 lsb max single-ended an d pseudo differential modes straight natural binary output coding offset error 1,2 7 lsb max offset error match 1,2 2 lsb typ gain error 1,2 2.5 lsb max gain error match 1,2 0.5 lsb typ twos complement output coding positive gain error 1,2 2 lsb max positive gain error match 1,2 0.5 lsb typ zero code error 1,2 5 lsb max zero code error match 1,2 1 lsb typ negative gain error 1,2 2 lsb max negative gain error match 1,2 0.5 lsb typ conversion rate conversion time 14 adsclk cycles 437.5 ns with adsclk = 32 mhz track-and-hold acquisition time 2 90 ns max full-scale step input; av dd , dv dd = 5 v 110 ns max full-scale step input; av dd , dv dd = 3 v throughput rate 2 msps max 1 see adcterminology on page 60 . 2 sample tested during initial release to ensure compliance. 3 guaranteed no missed codes to 12 bits. table 49. operating conditions (power 1 ) parameter specification unit test conditions/comments power supply requirements v dd 2.7/5.25 v min/v max v drive 2.7/5.25 v min/v max i dd digital logic inputs = 0 v or v drive normal mode (static) 2.3 ma max v dd = 5.25 v operational f s = 2 msps 6.4 ma max v dd = 5.25 v; 5.7 ma typ f s = 1.5 msps 4 ma max v dd = 3.6 v; 3.4 ma typ partial power-down mode 500 a max static full power-down mode (v dd )2.8 a maxstatic power dissipation normal mode (operational) 33.6 mw max v dd = 5.25 v partial power-down (static) 2.625 mw max v dd = 5.25 v full power-down (static) 14.7 w max v dd = 5.25 v 1 in this table, v dd refers to both av dd and dv dd . table 48. operating condit ions (adc performance/accuracy) (continued) parameter specification unit test conditions/comments rev. a | page 57 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adctiming specifications adcabsolute maximum ratings stresses above those listed in table 51 may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. table 50. serial data interface 1 1 see figure 87 on page 71 and figure 88 on page 71 . parameter specification unit test conditions / comments f adsclk 2 2 minimum adsclk for specified performance; with slower adsclk frequencies, perf ormance specificatio ns apply typically. 1/32 mhz min/max t convert 14 t adsclk ns max t adsclk = 1/f adsclk 437.5 ns max f adsclk = 32 mhz, f sample = 2 msps; av dd , dv dd = 5 v 560.0 ns max f adsclk = 25 mhz, f sample = 1.56 msps; av dd , dv dd = 3 v 583.3 ns max f adsclk = 24 mhz, f sample = 1.5 msps; av dd , dv dd = 2.7 v t quiet 30 ns min minimum time between end of serial read and next falling edge of cs t 2 18/23 ns min cs to adsclk setup time; v dd = 5 v/3 v t 3 15 ns max delay from cs until d out a and d out b are three-state disabled t 4 3 3 the time required for the ou tput to cross 0.4 v or 2.4 v. 27/36 ns max data access time after adsclk falling edge, v dd = 5 v/3 v t 5 0.45 t adsclk ns min adsclk low pulse width t 6 0.45 t adsclk ns min adsclk high pulse width t 7 5/10 ns min adsclk to data valid hold time, v dd = 5 v/3 v t 8 15 ns max cs rising edge to d out a, d out b, high impedance t 9 30 ns min cs rising edge to falling edge pulse width t 10 5/35 ns min/max adsclk falling edge to d out a, d out b, high impedance table 51. absolute maximum ratings parameter rating av dd , dv dd to agnd C0.3 v to +7 v dv dd to dgnd C0.3 v to +7 v v drive to dgnd C0.3 v to dv dd v drive to agnd C0.3 v to av dd av dd to dv dd C0.3 v to +0.3 v agnd to dgnd C0.3 v to +0.3 v analog input voltage to agnd C0.3 v to av dd + 0.3 v digital input voltage to dgnd C0.3 v to +7 v digital output voltage to gnd C0.3 v to v drive + 0.3 v v ref to agnd C0.3 v to av dd + 0.3 v input current to any adc pin except supplies 1 1 transient currents of up to 100 ma will not cause latch up. 10 ma storage temperature range see table 20 on page 30 junction temperature under bias see table 20 on page 30 rev. a | page 58 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adctypical performance characteristics t a = 25c, unless otherwise noted. figure 50. psrr vs. supply ripple fr equency without supply decoupling figure 51. channel-to -channel isolation figure 52. sinad vs. analog input frequency for various supply voltages supply ripple frequency (khz) 2000 0 200 400 600 800 1000 1200 1400 1600 1800 psrr (db) C60 C70 C80 C90 C100 C110 C120 100mv p-p sine wave on av dd no decoupling single-ended mode external reference internal reference noise frequency (khz) 1000 0 100 200 300 400 500 600 800 700 900 isolation (db) C 50 C 55 C 60 C 65 C 70 C 75 C 90 C 95 C 80 C 85 C 100 v dd = 5v input frequency (khz) 3000 0 1000 2000 500 1500 2500 sinad (db) 74 72 68 70 66 62 64 60 v dd = 5v differential mode v dd = 3v differential mode range = 0 to v ref f 53. tp fft f 54. tp dnl f 55. tp inl frequency (khz) 1000 0 100 200 300 400 500 600 700 800 900 (db) C10 C30 C50 C70 C90 C110 4096 point fft v dd = 5v, v drive = 3v f sample = 2msps f in = 52khz sinad = 71.4db thd = C84.42db differential mode code 4000 0 1000 2000 3000 3500 500 1500 2500 dnl error (lsb) 1.0 0.6 0.8 0.2 0.4 C0.2 0 C0.6 C0.8 C0.4 C1.0 v dd = 5v, v drive = 3v differential mode code 4000 0 500 1000 1500 2000 2500 3000 3500 inl error (lsb) 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v dd = 5v, v drive = 3v differential mode rev. a | page 59 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 56. linearity error vs. v ref figure 57. effective number of bits vs. v ref figure 58. v ref vs. reference output current drive v ref (v) 2.5 0 0.5 1.0 1.5 2.0 linearity error (lsb) 1.0 0.6 0.8 0.2 0.4 C0.2 0 C0.6 C0.4 C1.0 C0.8 v dd = 3v/5v differential mode positive inl positive dnl negative dnl negative inl v ref (v) 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 effective number of bits 12.0 11.0 11.5 10.0 10.5 9.0 9.5 8.0 7.5 8.5 7.0 v dd = 5v differential mode v dd = 3v differential mode v dd = 3v single-ended mode v dd = 5v single-ended mode current load ( a) 200 0 20 40 60 80 100 120 140 160 180 v ref (v) 2.5010 2.5000 2.5005 2.4995 2.4990 2.4985 2.4980 f 59. htm cd 10k smp dt md f 60. htm cd 10k smp s-edd md f 61. cmrr . cmm -md rpp f code 2046 2047 2049 2048 2050 no. of occurrences 10000 8000 9000 6000 7000 4000 5000 2000 1000 3000 0 10000 codes differential mode internal reference code 2046 2047 2048 2049 2050 no. of occurrences 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 9984 codes single-ended mode internal reference 5 codes 11 codes ripple frequency (khz) 1200 0 200 400 600 800 1000 cmrr (db) C60 C65 C70 C75 C80 C85 C95 C90 C100 differential mode v dd = 3v/5v rev. a | page 60 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f adcterminology differential nonlinearity (dnl) differential nonlinearity is the difference between the mea- sured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc trans- fer function. the endpoints of th e transfer func tion are zero scale with a single (1) lsb point below the first code transi- tion, and full scale with a 1 lsb point above the last code transition. offset error offset error applies to straight binary output coding. it is the deviation of the first code transition (00...000) to (00 . . . 001) from the ideal (agnd + 1 lsb). offset error match offset error match is the difference in offset error across all 12 channels. gain error gain error applies to straight binary output coding. it is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (v ref 1 lsb) after the offset error is adjusted out. gain error do es not include reference error. gain error match gain error match is the differen ce in gain error across all 12 channels. positive gain error this applies when using twos complement output coding with, for example, the 2 v ref input range as Cv ref to +v ref biased about the v ref point. it is the deviation of the last code transition (011110) to (011111) from the ideal (+v ref C 1 lsb) after the zero code error is adjusted out. positive gain error match this is the difference in posi tive gain error across all 12 channels. zero code error zero code error applies when using twos complement output coding with, for example, the 2 v ref input range as Cv ref to +v ref biased about the v ref point. it is the deviation of the mid-scale transition (all 0s to all 1s) from the ideal v in voltage (v ref ). zero code error match zero code error match refers to the difference in zero code error across all 12 channels. negative gain error this applies when using twos complement output coding option, in particular the 2 v ref input range as Cv ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100000) to (100001) from the ideal (that is, Cv ref + 1 lsb) after the zero code error is adjusted out. negative gain error match this is the difference in ne gative gain error across all 12 channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode after the end of conversion. track-and-ho ld acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal-to-(noise + dist ortion) ratio (sinad) this ratio is the measured ratio of signal-to-(noise + distor- tion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all non- fundamental signals up to ha lf the sampling frequency (f s /2), excluding dc. the ratio is depe ndent on the number of quan- tization levels in the digitalization process; the more levels, the smaller the quantization noise. the theoretical signal-to- (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to- ( noise + distortion ) = (6.02n + 1.76) db therefore, for a 12-bit converte r, theoretical sinad is 74 db. total harmonic distortion (thd) total harmonic distortion is th e ratio of the rms sum of har- monics to the fundamental. for the adc, it is defined as: where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. effective number of bits (enob) this is a figure of merit which characterizes the dynamic per- formance of the adc at a specified input frequency and sampling rate. enob is expresse d in bits. for a full scale sinu- soidal input, enob is defined as: enob = ( sinad C 1.76)/6.02 peak harmonic or spurious noise (sfdr) peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next larg est component in the adc out- put spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally , the value of this specification is determined by the largest harm onic in the spectrum, but for adcs where the harmonics are buri ed in the noise floor, it is a noise peak. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale (2 v ref when v dd = 5 v, v ref when v dd = 3 v), 10 khz sine wave signal to all un-selected input channels and 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = rev. a | page 61 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f determining how much that si gnal is attenuated in the selected channel with a 50 khz signal (0 v to v ref ). the result obtained is the wors t-case across all 12 channels for the adc. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active device with non-linearities create distortion products at sum, and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa fb), while the third-order terms include (2fa + fb), (2fa fb), (fa + 2fb), and (fa 2fb). the adc is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the se cond-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second-order and third-order terms are speci- fied separately. the calculat ion of the inter-modulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of th e fundamentals expressed in dbs. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in of frequency f s as: cmrr (db) = 10 log( pf/pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full-scale transition but not the converters linearity. psrr is the maximum change in the full-scale transition point du e to a change in power supply voltage from the nominal value (see figure 50 ( psrr vs. sup- ply ripple frequency without supply decoupling ). thermal hysteresis thermal hysteresis is defined as the absolute maximum change of reference output voltage (v ref ) after the device is cycled through temperature from either: t_hys+ = +25c to t max to +25c or t_hys = +25c to t min to +25c it is expressed in ppm by: where: v ref (25c) is v ref at 25c. v ref (t_hys) is the maximum change of v ref at t_hys+ or t_hys. adctheory of operation the following sections describe the adc theory of operation. circuit information the adc is a fast, micropower, dual, 12-bit, single-supply, adc that operates from a 2.7 v to a 5.25 v supply. when oper- ated from a 5 v supply, the adc is capable of th roughput rates of up to 2 msps when provided with a 32 mhz clock, and a throughput rate of up to 1.5 msps at 3 v. the adc contains two on-chip, differential track-and-hold amplifiers, two successive approximation adcs, and a serial interface with two separate data output pins. the serial clock input accesses da ta from the part but also pro- vides the clock source for each successive approximation adc. the analog input range for the part can be selected to be a 0 v to v ref input or a 2 v ref input, configured with either single- ended or differential analog inputs. the adc has an on-chip 2.5 v reference that can be overdriven when an external refer- ence is preferred. if the internal reference is to be used elsewhere in a system, then the output needs to buffered first. the adc also features power-down options to allow power sav- ing between conversions. the power-down feature is implemented via the standard seri al interface, as described in the adcmodes of operation section. converter operation the adc has two successive appr oximation adcs, each based around two capacitive dacs. figure 62 ( adc acquisition phase ) and figure 63 ( adc conversion phase ) show simplified schematics of one of these adcs in acquisition and conversion phase, respectively. the adc is comprised of control logic, a sar, and two capacitive dacs. in figure 62 ( adc acquisition phase ) (the acquisition phase), sw3 is closed, sw1 and sw2 are in position a, the co mparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 6 10 ) c 25 ( ) _ ( ) c 25 ( ) ( ? = ref ref ref hys v hys t v v ppm v figure 62. adc acquisition phase capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v inC v ref rev. a | page 62 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f when the adc starts a conversion (see figure 63 ( adc con- version phase )), sw3 opens and sw 1 and sw2 move to position b, causing the comparat or to become unbalanced. both inputs are disconnected once the conversion begins. the con- trol logic and the charge redist ribution dacs ar e used to add and subtract fixed amounts of ch arge from the sampling capaci- tor arrays to bring the compar ator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v in+ and v inC pins must be matched; otherwis e, the two inputs will have dif- ferent settling times, resulting in errors. analog input structure figure 64 ( equivalent analog inpu t circuit, conversion phaseswitches open, track phaseswitches closed ) shows the equivalent circuit of the an alog input structure of the adc in differential/pseudo differential mode. in single-ended mode, v in is internally tied to agnd . the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals ne ver exceed the supply rails by more than 300 mv. this causes these diodes to become for- ward-biased and starts conducti ng into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the c1 capacitors in figure 64 ( equivalent analog input cir- cuit, conversion phaseswitches open, track phase switches closed ) are typically 4 pf and can primarily be attrib- uted to pin capacitance. the re sistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the adcs sampling capacitors with a capacitance of 45 pf typically. for ac applications, removing high frequency components from the analog input signal is reco mmended by the use of an rc low-pass filter on the relevant analog input pins with optimum values of 47 and 10 pf. in applications where harmonic dis- tortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and may necessitate the use of an input buffer amplifier. the choice of the op amp is a functi on of the particular application. when no amplifier is used to dr ive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on th e amount of thd that can be tolerated. the thd increases as the source impedance incr eases and per- formance degrades. figure 65 ( thd vs. analog input frequency for various source impedances, single-ended mode shows a graph of the thd vs. the analog input signal frequency for different source impedances in single-ended mode, while figure 66 ( thd vs. analog input frequency for various source impedances, differential mode ) shows the thd vs. the analog input signal frequency for differen t source impedances in differ- ential mode. figure 67 ( thd vs. analog input frequency for various supply voltages ) shows a graph of the thd vs. the analog input fre- quency for various supplies whil e sampling at 2 msps. in this case, the source impedance is 47 . figure 63. adc conversion phase figure 64. equivalent analog input circuit, conversion phaseswitches open , track phaseswitches closed capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v inC v ref v dd c1 d d v in+ r1 c2 v dd c1 d d v inC r1 c2 f 65. thd . a ipt f v s impd, s-edd md input frequency (khz) 600 0 200 100 400 300 500 thd (db) C50 C60 C55 C65 C70 C75 C80 C85 C90 f sample = 1.5msps v dd = 3v range = 0v to v ref r source = 300 r source = 0 r source = 10 r source = 47 r source = 100 rev. a | page 63 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f analog inputs the adc has a total of 12 analog inputs. each on-board adc has six analog inputs that can be configured as six single-ended channels, three pseudo differentia l channels, or three fully dif- ferential channels. these may be selected as described in the analog input selection section. single-ended mode the adc can have a total of 12 single-ended analog input chan- nels. in applications where the signal source has high impedance, it is recommended to buffer the analog input before applying it to the adc. the analog input range can be programmed to be either 0 to v ref or 0 to 2 v ref . if the analog input signal to be sampled is bipolar, the internal reference of the adc can be used to externally bias up this sig- nal to make it correctly formatted for the adc. figure 68 shows a typical connection diagram wh en operating the adc in sin- gle-ended mode. differential mode the adc can have a total of six differential analog input pairs. differential signals have some benefits over single-ended sig- nals, including noise immunity based on the devices common- mode rejection and improvements in distortion performance. figure 69 ( differential input definition ) defines the fully differ- ential analog input of the adc. the amplitude of the differential signal is the difference between the signals applied to the v in+ and v inC pins in each differential pair (v in+ v inC ). v in+ and v inC should be simultaneously driven by two signals each of amplitude v ref (or 2 v ref , depending on the range chosen) that are 180 out of phase. the amplitude of the differential signal is, therefore (assuming the 0 to v ref range is selected) Cv ref to +v ref peak-to-peak (2 v ref ), regardless of the co mmon mode (cm). the common mode is the average of the two signals ( v in+ + v inC )/2 and is, therefore, the voltage on which the two inputs are centered. this results in the span of each input being cm v ref /2. this voltage has to be set up externa lly and its range varies with the reference value, v ref . as the value of v ref increases, the com- mon-mode range decreases. when driving the inputs with an amplifier, the actual common-mode range is determined by the amplifiers output voltage swing. figure 70 ( input common-mode range vs. vref (0 to vref range, vdd = 5 v) ) and figure 71 ( input common-mode range vs. vref (2 vref range, vdd = 5 v) ) show how the common-mode range typi cally varies with v ref for a 5 v power figure 66. thd vs. analog input frequency for various source impedanc es, differential mode figure 67. thd vs. analog input frequency for various supply voltages input frequency (khz) 600 700 800 900 1000 0 200 100 400 300 500 thd (db) C60 C65 C70 C75 C80 C85 C90 f sample = 1.5msps v dd = 3v range = 0v to v ref r source = 300 r source = 0 r source = 10 r source = 47 r source = 100 input frequency (khz) 600 700 800 900 1000 0 200 100 400 300 500 thd (db) C50 C60 C55 C65 C70 C75 C80 C85 C90 v dd = 3v single-ended mode v dd = 5v single-ended mode v dd = 3v differential mode v dd = 5v differential mode f sample = 1.5msps/2msps v dd = 3v/5v range = 0 to v ref f 68. s-edd md ct dm f 69. dt ipt dt v in 0v +1.25v C1.25v v ref (d cap a/d cap b) v a1 adc 1 v b6 r r 3r r 0v +2.5v 0.47 f 1 additional pins omitted for clarity. v in+ adc 1 v inC v ref p-p v ref p-p common mode voltage 1 additional pins omitted for clarity. rev. a | page 64 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f supply using the 0 to v ref range or 2 v ref range, respectively. the common mode must be in th is range to guarantee the func- tionality of the adc. when a conversion takes place, the common mode is rejected, resulting in a virtually nois e free signal of amplitude Cv ref to +v ref corresponding to the digital codes of 0 to 4096. if the 2 v ref range is used, then the input signal amplitude extends from C 2 v ref to +2 v ref after conversion. driving differential inputs differential operation requires that v in+ and v inC be simultane- ously driven with two equal signal s that are 180 out of phase. the common mode must be set up externally. the common- mode range is determined by v ref , the power supply, and the particular amplifier used to drive the analog inputs. differential modes of operation with either an ac or dc input provide the best thd performance over a wi de frequency range. because not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-dif- ferential conversion. using an op amp pair an op amp pair can be used to di rectly couple a differential sig- nal to one of the analog input pairs of the adc. the circuit configurations illustrated in figure 72 ( dual op amp circuit to convert a single-ended unipolar signal into a differential sig- nal ) and figure 73 ( dual op amp circuit to convert a single- ended bipolar signal into a differential unipolar signal ) show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. the voltage applied to point a sets up the common-mode volt- age. in both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the comm on mode. the ad8022 is a suit- able dual op amp that can be used in this configuration to provide differential drive to the adc. take care when choosing the op amp; the selection depends on the required power supply and sy stem performance objectives. the driver circuits in figure 72 ( dual op amp circuit to con- vert a single-ended unipolar si gnal into a differential signal ) and figure 73 ( dual op amp circuit to convert a single-ended bipolar signal into a differential unipolar signal ) are optimized for dc coupling applications requiring best distortion performance. the circuit configuration shown in figure 72 ( dual op amp circuit to convert a single-ended unipolar signal into a differ- ential signal ) converts a unipolar, sing le-ended signal into a differential signal. the differential op amp driver circuit shown in figure 73 ( dual op amp circuit to convert a sing le-ended bipolar signal into a differential unipolar signal ) is configured to convert and level shift a single-ended, ground-refer enced (bipolar) signal to a dif- ferential signal centered at the v ref level of the adc. pseudo differential mode the adc can have a total of six ps eudo differential pairs. in this mode, v in+ is connected to the signal source that must have an amplitude of v ref (or 2 v ref , depending on the range chosen) figure 70. input comm on-mode range vs. v ref (0 to v ref range, v dd = 5 v) figure 71. input common-mode range vs. v ref (2 v ref range, v dd = 5 v) v ref (v) 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 common-mode range (v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25c v ref (v) 2.5 0 0.5 1.0 1.5 2.0 common-mode range (v) 5.0 4.0 4.5 3.0 3.5 2.0 2.5 0.5 1.0 1.5 0 t a = 25c f 72. d op amp ct t ct s-edd up s it dt s gnd 2 v ref pCp 27 27 v+ vC v+ vC v ref 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v v ref (d cap a/d cap b) v in+ adc 1 v inC 440 220 0.47 f 1 additional pins omitted for clarity. 220 220 10k a rev. a | page 65 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f to make use of the full dynamic ra nge of the part. a dc input is applied to the v inC pin. the voltage applied to this input pro- vides an offset from ground or a pseudo ground for the v in+ input. the benefit of pseudo differe ntial inputs is that they sepa- rate the analog input signal ground from the adcs ground allowing dc common-mode vo ltages to be cancelled. the typical voltage range for the v inC pin, while in pseudo dif- ferential mode, is shown in figure 74 ( v inC input voltage range vs. v ref in pseudo differential mode with v dd = 3 v ) and figure 75 ( v inC input voltage range vs. v ref in pseudo differ- ential mode with v dd = 5 v ). figure 76 ( pseudo differential mode connection diagram ) shows a connecti on diagram for pseudo differential mode. analog input selection the analog inputs of the adc can be configured as single- ended or true differential via the sgl/diff logic pin, as shown in figure 77 ( selecting differential or single-ended configura- tion ). if this pin is tied to a logi c low, the analog input channels to each on-chip adc are set up as three true differential pairs. if this pin is at logic high, the an alog input channels to each on- chip adc are set up as six si ngle-ended analog inputs. the required logic level on this pin needs to be established prior to the acquisition time and remain unchanged during the conver- sion time until the track-and-ho ld has returned to track. the track-and-hold return s to track on the 13 th rising edge of adsclk after the cs falling edge (see figure 87 ( serial inter- face timing diagram )). if the level on this pin is changed, it will be recognized by the adc; therefor e, it is necessary to keep the same logic level during acquisit ion and conversion to avoid cor- rupting the conversion in progress. for example, in figure 77 ( selecting differential or single- ended configuration ) the sgl/diff pin is set at logic high for the duration of both the acquisit ion and conversion times so the analog inputs are configured as single ended for that conversion (sampling point a). the lo gic level of the sgl/diff changed to low after the track-and-hold retu rned to track and prior to the figure 73. dual op amp circuit to co nvert a single-ended bipolar signal into a differential unipolar signal figure 74. v in- input voltage range vs. v ref in pseudo differential mode with v dd = 3 v 20k 220k 2 v ref pCp 27 27 v+ vC v+ vC gnd 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v v in+ adc 1 v inC 440 220 0.47 f 1 additional pins omitted for clarity. 220 220 10k a v ref (d cap a/d cap b) v ref (v) 3.0 0 0.5 1.0 1.5 2.0 2.5 v inC (v) 1.0 0.8 0.4 0.6 0.2 C0.2 0 C0.4 t a = 25c f 75. v inC ipt vt r . v ref pd dt md t v dd = 5 v f 76. pd dt md ct dm v ref (v) 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v inC (v) 2.5 2.0 1.5 1.0 0.5 0 C0.5 t a = 25c dc input voltage v ref pCp v ref ( d cap a/d cap b) v in+ adc 1 v inC 0.47 f 1 additional pins omitted for clarity. rev. a | page 66 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f required acquisition time for the next sampling instant at point b; therefore, the analog inputs are configured as differential for that conversion. the channels used for simultaneo us conversions are selected via the multiplexer address input pins, a0 to a2. the logic states of these pins also need to be esta blished prior to the acquisition time; however, they may change during the conversion time provided the mode is not changed. if the mode is changed from fully differential to pseudo diffe rential, for example, then the acquisition time would start again from this point. the selected input channels are de coded as shown in table 53 ( analog input type and channel selection ). the analog input range of the adc can be selected as 0 v to v ref or 0 v to 2 v ref via the range pin. this selection is made in a similar fashion to that of the sgl/diff pin by setting the logic state of the range pin a time t acq prior to the falling edge of cs . subsequent to this, the logic level on this pin can be altered after the third falling edge of adsclk. if this pin is tied to a logic low, the analog input range selected is 0 v to v ref . if this pin is tied to a logic high, the analog input range selected is 0 v to 2 v ref . output coding the adc output coding is set to either twos complement or straight binary, depending on which analog input configuration is selected for a conversion. table 52 ( adc output coding ) shows which output coding sche me is used for each possible analog input configuration. transfer functions the designed code transitions occur at successive integer lsb values (1 lsb, 2 lsb, and so on). in single-ended mode, the lsb size is v ref /4096 when the 0 v to v ref range is used, and the lsb size is 2 v ref /4096 when the 0 v to 2 v ref range is used. in differential mode, the lsb size is 2 v ref /4096 when the 0 v to v ref range is used, and the lsb size is 4 v ref /4096 when the 0 v to 2 v ref range is used. the ideal tr ansfer characteristic for the adc when straight binary coding is output is shown in figure 78 ( straight binary transfer characteristic ), and the ideal transfer characteristic for the adc when twos comple- ment coding is output is shown in figure 79 ( twos complement transfer characteri stic with vref vref input range ) (this is shown with the 2 v ref range). figure 77. selecting differential or single-ended configuration adsclk cs 114 14 1 a sgl/diff b t acq table 52. adc output coding sgl/diff range output coding 0 (differential input) 0 (0 v to v ref ) twos complement 0 (differential input) 1 (0 v to 2 v ref ) twos complement 1 (single-ended input) 0 (0 v to v ref ) straight binary 1 (single-ended input) 1 (0 v to2 v ref ) twos complement 0 (pseudo-differential input) 0 (0 v to v ref ) straight binary 0 (pseudo-differential input) 1 (0 v to 2 v ref ) twos complement table 53. analog input type and channel selection adc a adc b sgl/diff a2 a1 a0 v in+ v inC v in+ v inC comment 1000v a1 agnd v b1 agnd single ended 1001v a2 agnd v b2 agnd single ended 1010v a3 agnd v b3 agnd single ended 1011v a4 agnd v b4 agnd single ended 1100v a5 agnd v b5 agnd single ended 1101v a6 agnd v b6 agnd single ended 0000v a1 v a2 v b1 v b2 fully differential 0001v a1 v a2 v b1 v b2 pseudo differential 0010v a3 v a4 v b3 v b4 fully differential 0011v a3 v a4 v b3 v b4 pseudo differential 0100v a5 v a6 v b5 v b6 fully differential 0101v a5 v a6 v b5 v b6 pseudo differential rev. a | page 67 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f serial interface voltage drive the adc also has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the adc was operated with a av dd /dv dd of 5 v, the v drive pin could be powered from a 3 v supply, best adc performance low voltage digital processors. therefore, the adc could be used with the 2 v ref input range, with a av dd /dv dd of 5 v while still being able to serial interface to 3 v digital i/o parts. adcmodes of operation the mode of operation of the adc is selected by controlling the (logic) state of the cs signal during a conversion. there are three possible modes of operation: normal mode, partial power- down mode, and full power-down mode. after a conversion is initiated, the point at which cs is pulled high determines which power-down mode, if any, the devi ce enters. similarly, if already in a power-down mode, cs can control whether the device returns to normal operation or remains in power-down. these modes of operation are designed to provide flexible power man- agement options. these options can be chosen to optimize the power dissipation/throu ghput rate ratio fo r differing applica- tion requirements. normal mode this mode is intended for applications needing fastest through- put rates because the user does not have to worry about any power-up times with the adc remaining fully powered at all times. figure 80 ( normal mode operation ) shows the general diagram of the operation of the adc in this mode. the conversion is initiated on the falling edge of cs , as described in the adcserial interface section. to ensure that the part remains fully powered up at all times, cs must remain low until at least 10 adsclk falli ng edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10 th adsclk falling edge but before the 14 th adsclk falling edge, the part remains powered up, but the conversion is terminated and d out a and d out b go back into three-state. fourteen serial clock cycles are required to comp lete the conversion and access the conversion result. the d out line does not return to three- state after 14 adsclk cycles have elapsed, but instead does so when cs is brought high again. if cs is left low for another 2 adsclk cycles (for example, if only a 16 adsclk burst is available), two trailing zeros are clocked out after the data. if cs is left low for a further 14 (or16) adsclk cycles, the result from the other adc on board is also accessed on the same d out line, as shown in figure 88 ( reading data from both adcs on one dout line with 32 adsclks ). see the adcserial interface section. once 32 adsclk cycles have elapsed, the d out line returns to three-state on the 32 nd adsclk falling edge. if cs is brought high prior to this, the d out line returns to three-state at that point. therefore, cs may idle low after 32 adsclk cycles until it is brought high again sometime prior to the next conversion (effectively idling cs low), if so desired, because the bus still returns to three-state upon comple tion of the dual result read. once a data transfer is complete and d out a and d out b have returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again (assuming the required acquisition time is allowed). partial power-down mode this mode is intended for use in applications where slower throughput rates are required. ei ther the adc is powered down between each conversion, or a series of conversions may be per- formed at a high throughput ra te, and the adc is then powered figure 78. straight binary transfer characteristic figure 79. twos complement tr ansfer characteristic with v ref v ref input range 000...000 111...111 1lsb = v ref /4096 1lsb v ref C 1lsb analog input adc code 0v 000...001 000...010 111...110 111...000 011...111 note 1. v ref is either v ref or 2 v ref . 100...000 011...111 1lsb = 2 v ref /4096 +v ref C 1 lsb Cv ref + 1lsb v ref C 1lsb analog input adc code 100...001 100...010 011...110 000...001 000...000 111...111 f 80. nm md opt adsclk leading zeros + conversion result cs d out a d out b 114 10 rev. a | page 68 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f down for a relatively long durati on between these bursts of sev- eral conversions. when the adc is in partial power-down, all analog circuitry is powered down except for the on-chip refer- ence and reference buffer. to enter partial power-down mode, the conversion process must be interrupted by bringing cs high anywhere after the sec- ond falling edge of adsclk and before the 10 th falling edge of adsclk, as shown in figure 81 ( entering partial power-down mode ). once cs is brought high in th is window of adsclks, the part enters partial power-do wn, the conversion that was ini- tiated by the falling edge of cs is terminated, and d out a and d out b go back into three-state. if cs is brought high before the second adsclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power-down due to glitches on the cs line. to exit this mode of operation and power up the adc again, a dummy conversion is performed. on the falling edge of cs , the device begins to power up and co ntinues to power up as long as cs is held low until after the falling edge of the 10 th adsclk. the device is fully powered up after approximately 1 s has elapsed, and valid data results from the next conversion, as shown in figure 82 ( exiting partial power-down mode ). if cs is brought high before the seco nd falling edge of adsclk, the adc again goes into partial po wer-down. this avoids acciden- tal power-up due to glitches on the cs line. although the device may begin to power up on the falling edge of cs , it powers down again on the rising edge of cs . if the adc is already in partial power-down mode and cs is brought high between the second and 10 th falling edges of adsclk, th e device enters full power- down mode. full power-down mode this mode is intended for use in applications where throughput rates slower than those in th e partial power- down mode are required, as power-up from a full power-down takes substan- tially longer than th at from partial power-down. this mode is more suited to applications where a series of conversions per- formed at a relatively high th roughput rate are followed by a long period of inactivity and thus power-down. when the adc is in full power-down, all analog circuitry is powered down. full power-down is entered in a similar way as partial power-down, except the timing sequence shown in figure 81 ( entering partial power-down mode ) must be executed twice. the conversion process must be interrupted in a similar fashion by bringing cs high anywhere after the second falling edge of adsclk and before the 10 th falling edge of adsclk. the device enters par- tial power-down at this point. to reach full power-down, the next conversion cycle must be in terrupted in the same way, as shown in figure 83 ( entering full power-down mode ). once cs is brought high in this wind ow of adsclks, the part com- pletely powers down. note that it is not necessary to complete the 14 adsclks once cs is brought high to enter a power-down mode. to exit full power-down and po wer up the adc, a dummy con- version is performed, as when powering up from partial power- down. on the falling edge of cs , the device begins to power up and continues to power up, as long as cs is held low until after the falling edge of the 10 th adsclk. the required power-up time must elapse before a conver sion can be initiated, as shown in figure 84 ( exiting full power-down mode ). see the power- up times section for the po wer-up times associated with the adc. figure 81. entering partial power-down mode adsclk three-state cs d out a d out b 114 10 2 f 82. et pt p-d md adsclk cs d out a d out b invalid data valid data 11014 14 1 the part begins to power up. the part is fully powered up; see power-up times section. t power-up1 rev. a | page 69 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f power-up times as described in detail, the adc has two power-down modes, partial power-down and full po wer-down. this section deals with the power-up time required when coming out of either of these modes. it should be noted that the power-up times, as explained in this section, appl y with the recommended capaci- tors in place on the d cap a and d cap b pins. to power up from full power- down, approximately 1.5 ms should be allowed from the falling edge of cs , shown as t power-up2 in figure 84 ( exiting full power-down mode ). pow- ering up from partia l power-down requires much less time. the power-up time from partial power-down is typically 1 s; how- ever, if using the internal refere nce, then the adc must be in partial power-down for at least 67 s in order for this power-up time to apply. when power supplies are first applied to the adc, the adc may power up in either of th e power-down modes or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powe red up before attempting a valid conversion. likewise, if it is inte nded to keep the part in the par- tial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th adsclk falling edge (see figure 80 ( normal mode operation )); in the second cycle, cs must be brought high before the 10 th adsclk edge but after the second adsclk falling edge (see figure 81 ( entering partial power-down mode )). alternatively, if it is intended to place the part in full power-down mode when the supplies are applied, then three du mmy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th adsclk falling edge (see figure 80 ( normal mode opera- tion )); the second and third dummy cycles place the part in full power-down (see figure 83 ( entering full power-down mode )). once supplies are applied to th e adc, enough time must be allowed for any external reference to power up and charge the various reference buffer decoupli ng capacitors to their final values. power vs. throughput rate the power consumption of the adc varies with the throughput rate. when using very slow throughput rates and as fast an adsclk frequency as possibl e, the various power-down options can be used to make significant power savings. how- ever, the adc quiescent current is low enough that even without using the power-down op tions, there is a noticeable variation in power cons umption with sampling rate. this is true whether a fixed adsclk value is used or if it is scaled with the sampling rate. figure 85 ( power vs. throughput in normal mode with vdd = 3 v ) and figure 86 ( power vs. throughput in normal mode with vdd = 5 v ) show plots of power vs. the throughput rate when operating in normal mode for a fixed figure 83. entering full power-down mode figure 84. exiting full power-down mode three-state 11014 2 adsclk cs d out a d out b three-state 11014 2 invalid data invalid data the part begins to power up. the part enters partial power down. the part enters full power down. adsclk d out a d out b invalid data valid data 1 10 14 14 1 the part begins to power up. the part is fully powered up, see power-up times section. t power-up2 cs rev. a | page 70 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f maximum adsclk frequency and an adsclk frequency that scales with the sampling rate with v dd = 3 v and v dd = 5 v, respectively. in all cases, the internal reference was used. adcserial interface figure 87 ( serial interface timing diagram ) shows the detailed timing diagram for serial interf acing to the adc. the serial clock provides the conversion cloc k and controls the transfer of information from the adc during conversion. the cs signal initiates the data tran sfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. the conversion is also initiated at this point and requires a minimum of 14 adsclks to complete. once 13 adsclk falling edges have elap sed, the track-and-hold goes back into track on the next ad sclk rising edge, as shown in figure 87 ( serial interface timing diagram ) at point b. if a 16 adsclk transfer is used, then two trailing zeros appear after the final lsb. on the rising edge of cs , the conversion is termi- nated and d out a and d out b go back into three-state. if cs is not brought high but is instead held low for a further 14 (or 16) adsclk cycles on d out a, the data from conversion b is out- put on d out a (followed by two trailing zeros). likewise, if cs is held low for a further 14 (or 16) adsclk cycles on d out b, the data from conver sion a is output on d out b. this is illustrated in figure 88 ( reading data from both adcs on one dout line with 32 adsclks ) where the case for d out a is shown. in this case, the d out line in use goes back into three-state on the 32 nd adsclk falling edge or the rising edge of cs , whichever occurs first. a minimum of 14 serial clock cycl es are required to perform the conversion process and to access data from one conversion on either data line of the adc. cs going low provides the leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by su bsequent adsclk falling edges, beginning with a second leadin g zero. thus, the first falling clock edge on the serial clock ha s the leading zero provided and also clocks out the second lead ing zero. the 12-bit result then follows with the final bit in th e data transfer valid on the 14 th falling edge, having being clocked out on the previous (13 th ) fall- ing edge. in applications with a slower adsclk, it may be possible to read in data on each adsclk rising edge depending on the adsclk frequency. the first rising edge of adsclk after the cs falling edge would have the second leading zero provided, and the 13 th rising adsclk edge would have db0 provided. note that with fast adsclk values, and thus short adsclk periods, in order to allow adequately for t 2 , an adsclk rising edge may occur before the first adsclk falling edge. this ris- ing edge of adsclk may be ignored for the purposes of the timing descriptions in this section. if a falling edge of adsclk is coincident with th e falling edge of cs , then this falling edge of adsclk is not acknowledged by the adc, and the next falling edge of adsclk will be the first registered after the falling edge of cs . figure 85. power vs. throughput in normal mode with v dd = 3 v figure 86. power vs. throughp ut in normal mode with v dd = 5 v throughput (ksps) 1400 0 200 400 600 800 1000 1200 power (mw) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 24mhz adsclk variable adsclk t a = 25c throughput (ksps) 2000 0 200 400 600 800 1000 1200 1400 1600 1800 power (mw) 30 28 26 24 22 20 18 16 14 12 10 32mhz adsclk variable adsclk t a = 25c rev. a | page 71 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 87. serial interface timing diagram figure 88. reading data fr om both adcs on one d out line with 32 adsclks cs adsclk 1 5 13 d out a d out b 2 leading zeros three- state t 4 2 34 t 5 t 3 t quiet t 2 three-state db11 db10 db2 db0 t 6 t 7 t 8 0 0 db1 b db9 db8 t 9 cs adsclk 1 5 15 d out a three- state t 4 2 34 16 t 5 t 3 t 2 three- state t 6 t 7 14 zero 0 zero db11 b 17 2 leading zeros t 10 32 db11 a 2 leading zeros db10 a db9 a zero zero zero 2 trailing zeros zero zero 2 trailing zeros rev. a | page 72 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f 120-lead lqfp lead assignment table 54 lists the lqfp leads by signal mnemonic. table 55 on page 73 lists the lqfp leads by lead number. table 54. 120-lead lqfp lead assign ment (alphabetical by signal) signal lead no. signal lead no. signal lead no. signal lead no. a0 100 nc 72 pg11 46 v b5 88 a1 98 nmi 11 pg12 47 v b6 87 a2 97 pf0 118 pg13 48 v ddext 1 agnd 73 pf1 119 pg14 49 v ddext 6 agnd 78 pf2 2 pg15 50 v ddext 15 agnd 79 pf3 4 ph0 113 v ddext 20 agnd 82 pf4 3 ph1 115 v ddext 23 agnd 93 pf5 5 ph2 114 v ddext 26 agnd 99 pf6 7 range 95 v ddext 30 av dd 76 pf7 8 ref_select 75 v ddext 41 bmode0 58 pf8 9 reset 12 v ddext 51 bmode1 57 pf9 10 scl 55 v ddext 59 bmode2 56 pf10 14 adsclk 102 v ddext 62 clkin 110 pf11 16 sda 54 v ddext 64 cs 101 pf12 18 sgl/diff 96 v ddext 66 d cap a 77 pf13 19 tck 34 v ddext 67 d cap b 94 pf14 21 tdi 33 v ddext 112 dgnd 74 pf15 22 tdo 36 v ddext 116 dgnd 104 pg 71 tms 35 v ddflash 25 d out a 105 pg0 27 trst 37 v ddflash 63 d out b 103 pg1 28 v a1 80 v ddflash 69 dv dd 107 pg2 29 v a2 81 v ddint 24 emu 68 pg3 31 v a3 83 v ddint 42 ext_wake 70 pg4 32 v a4 84 v ddint 52 extclk 120 pg5 38 v a5 85 v ddint 53 gnd 13 pg6 39 v a6 86 v ddint 61 gnd 17 pg7 40 v b1 92 v ddint 65 gnd 108 pg8 43 v b2 91 v ddint 117 gnd 109 pg9 44 v b3 90 v drive 106 nc 60 pg10 45 v b4 89 xtal 111 gnd 121 * agnd 122 ** * pin no. 121 is the gnd supply (see figure 89 and figure 90 ) for the processor (4.6mm 6.17mm); this pad must connect to gnd. ** pin no. 122 is the agnd supply (see figure 89 and figure 90 ) for the adc (2.81mm 2.81mm); this pad must connect to agnd. rev. a | page 73 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 55. 120-lead lqfp lead assignme nt (numerical by lead number) lead no. signal lead no. signal lead no. signal lead no. signal 1v ddext 31 pg3 61 v ddint 91 v b2 2 pf2 32 pg4 62 v ddext 92 v b1 3pf4 33tdi 63v ddflash 93 agnd 4pf3 34tck 64v ddext 94 d cap b 5 pf5 35 tms 65 v ddint 95 range 6v ddext 36 tdo 66 v ddext 96 sgl/diff 7pf6 37trst 67 v ddext 97 a2 8 pf7 38 pg5 68 emu 98 a1 9 pf8 39 pg6 69 v ddflash 99 agnd 10 pf9 40 pg7 70 ext_wake 100 a0 11 nmi 41 v ddext 71 pg 101 cs 12 reset 42 v ddint 72 nc 102 adsclk 13 gnd 43 pg8 73 agnd 103 d out b 14 pf10 44 pg9 74 dgnd 104 dgnd 15 v ddext 45 pg10 75 ref_select 105 d out a 16 pf11 46 pg11 76 av dd 106 v drive 17 gnd 47 pg12 77 d cap a107 dv dd 18 pf12 48 pg13 78 agnd 108 gnd 19 pf13 49 pg14 79 agnd 109 gnd 20 v ddext 50 pg15 80 v a1 110 clkin 21 pf14 51 v ddext 81 v a2 111 xtal 22 pf15 52 v ddint 82 agnd 112 v ddext 23 v ddext 53 v ddint 83 v a3 113 ph0 24 v ddint 54 sda 84 v a4 114 ph2 25 v ddflash 55 scl 85 v a5 115 ph1 26 v ddext 56 bmode2 86 v a6 116 v ddext 27 pg0 57 bmode1 87 v b6 117 v ddint 28 pg1 58 bmode0 88 v b5 118 pf0 29 pg2 59 v ddext 89 v b4 119 pf1 30 v ddext 60 nc 90 v b3 120 extclk 121 * gnd 122 ** agnd * pin no. 121 is the gnd supply (see figure 89 and figure 90 ) for the processor (4.6mm 6.17mm); this pad must connect to gnd. ** pin no. 122 is the agnd supply (see figure 89 and figure 90 ) for the adc (2.81mm 2.81mm); this pad must connect to agnd. rev. a | page 74 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 89 shows the top view of the 120-lead lqfp package lead configuration. figure 90 shows the bottom view of the 120-lead lqfp package lead configuration. figure 89. 120-lead lqfp package lead configuration (top view) pin 1 pin 3 0 pin 90 pin 61 pin 120 pin 91 pin 3 1 pin 60 pin 1 120-lead lqfp top view indicator figure 90. 120-lead lqfp package lead configuration (bottom view) pin 3 0 pin 1 pin 61 pin 90 pin 3 1 pin 60 pin 120 pin 91 120-lead lqfp gnd agnd pad pad (pin 121) (pin 122) bottom view rev. a | page 75 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f 88-lead lfcsp lead assignment table 56 lists the lfcsp leads by signal mnemonic. table 57 on page 76 lists the lfcsp by lead number. table 56. 88-lead lfcsp lead assignment (alphabetical by signal) signal lead no. signal lead no. signal lead no. signal lead no. bmode0 51 pf4 82 pg9 34 v ddext 20 bmode1 50 pf5 83 pg10 35 v ddext 31 bmode2 49 pf6 85 pg11 36 v ddext 41 clkin 68 pf7 86 pg12 37 v ddext 52 emu 60 pf8 87 pg13 38 v ddext 54 ext_wake 62 pf9 88 pg14 39 v ddext 56 extclk 78 pf10 4 pg15 40 v ddext 58 gnd 3 pf11 6 ph0 71 v ddext 59 gnd 7 pf12 8 ph1 72 v ddext 70 gnd 67 pf13 9 ph2 73 v ddext 74 nc 45 pf14 11 reset 2v ddext 79 nc 46 pf15 12 scl 44 v ddext 84 nc 47 pg 63 sda 43 v ddflash 15 nc 48 pg0 17 tck 24 v ddflash 55 nc 64 pg1 18 tdi 23 v ddflash 61 nc 65 pg2 19 tdo 27 v ddint 14 nc 66 pg3 21 tms 25 v ddint 32 nmi 1pg4 22trst 26 v ddint 42 pf0 76 pg5 28 v ddext 5v ddint 53 pf1 77 pg6 29 v ddext 10 v ddint 57 pf2 80 pg7 30 v ddext 13 v ddint 75 pf3 81 pg8 33 v ddext 16 xtal 69 gnd 89 * * pin no. 89 is the gnd supply (see figure 92 ) for the processor; this pad must connect to gnd. rev. a | page 76 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f table 57. 88-lead lfcsp lead assignment (numerical by lead number) lead no. signal lead no. signal lead no. signal lead no. signal 1nmi 23 tdi 45 nc 67 gnd 2reset 24 tck 46 nc 68 clkin 3 gnd 25 tms 47 nc 69 xtal 4 pf10 26 trst 48 nc 70 v ddext 5v ddext 27 tdo 49 bmode2 71 ph0 6 pf11 28 pg5 50 bmode1 72 ph1 7 gnd 29 pg6 51 bmode0 73 ph2 8 pf12 30 pg7 52 v ddext 74 v ddext 9 pf13 31 v ddext 53 v ddint 75 v ddint 10 v ddext 32 v ddint 54 v ddext 76 pf0 11 pf14 33 pg8 55 v ddflash 77 pf1 12 pf15 34 pg9 56 v ddext 78 extclk 13 v ddext 35 pg10 57 v ddint 79 v ddext 14 v ddint 36 pg11 58 v ddext 80 pf2 15 v ddflash 37 pg12 59 v ddext 81 pf3 16 v ddext 38 pg13 60 emu 82 pf4 17 pg0 39 pg14 61 v ddflash 83 pf5 18 pg1 40 pg15 62 ext_wake 84 v ddext 19 pg2 41 v ddext 63 pg 85 pf6 20 v ddext 42 v ddint 64 nc 86 pf7 21 pg3 43 sda 65 nc 87 pf8 22 pg4 44 scl 66 nc 88 pf9 89 * gnd * pin no. 89 is the gnd supply (see figure 92 ) for the processor; this pad must connect to gnd. rev. a | page 77 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 91 shows the top view of the lfcsp pin configuration. figure 92 shows the bottom view of the lfcsp lead configuration. figure 91. 88-lead lfcsp lead configuration (top view) pin 1 pin 22 pin 66 pin 45 pin 88 pin 67 pin 2 3 pin 44 pin 1 88 -lead lfc s p top view indicator figure 92. 88-lead lfcsp lead configuration (bottom view) pin 66 pin 45 pin 1 pin 22 pin 67 pin 88 pin 46 pin 2 3 pin 1 88 -lead lfc s p gnd pad (pin 8 9) bottom view indicator rev. a | page 78 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f outline dimensions dimensions in figure 93 (for the 120-lead lqfp) and in figure 94 (for the 88-lead lfcsp) are shown in millimeters. figure 93. 120-lead low profile quad flat package, exposed pad [lqfp_ep] 1 (sw-120-2) dimensions shown in millimeters 1 for information relating to the sw-120-2 packages exposed pad, see the table endnote on page 73 . compliant to jedec standards ms-026-bee-hd 1.45 1.40 1.35 0.15 0.10 0.05 0.08 max coplanarity view a seating plane 12 7 0 0.20 0.15 0.09 1.60 max view a 0.75 0.60 0.45 1.00 ref top view (pins down) 91 1 90 31 30 60 61 120 16.20 16.00 sq 15.80 14.10 14.00 sq 13.90 pin 1 0.40 bsc lead pitch 0.23 0.18 0.13 31 91 61 90 120 30 1 60 bottom view (pins up) exposed pad exposed pad for proper connection of the exposed pad, refer to the lead assignment and signal descriptions sections of this data sheet. 0.77 ref 2.945 ref sq 4.60 ref 1.915 2.81 ref sq 1.53 6.17 ref rev. a | page 79 of 80 | july 2011 ADSP-BF504/ADSP-BF504f/adsp-bf506f figure 94. 88-lead lead frame chip scale package [lfcsp_vq] 1 12 x 12 mm body, very thin quad (cp-88-5) dimensions shown in millimeters 1 for information relating to the cp-88-5 pa ckages exposed pad, see the table endnote on page 75 . 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.30 0.23 0.18 10.50 ref 0.60 max 0.60 max 6.70 ref sq 0.50 bsc 0.138~0.194 ref 12 max seating plane top view exposed pad bottom view 0.85 0.80 0.75 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indicator 12.10 12.00 sq 11.90 11.85 11.75 sq 11.65 pin 1 indicator for proper connection of the exposed pad, refer to the lead assignment and signal descriptions sections of this data sheet. rev. a | page 80 of 80 | july 2011 ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08560-0-7/11(a) ADSP-BF504/ADSP-BF504f/adsp-bf506f automotive products the adbf504w model is availabl e with controlled manufactur- ing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models and designers should review the specifications section of this data sheet carefully. only the au tomotive grade products shown in table 58 are available for use in automotive applications. contact your local ad i account representative for specific product ordering information and to obtain the specific auto- motive reliability reports for these models. ordering guide table 58. automotive products automotive models 1,2 temperature range 3 processor instruction rate (maximum) flash memory package description package option adbf504wycpz4xx C40oc to +105oc 400 mhz n/a 88-lead lfcsp_vq cp-88-5 1 z = rohs compliant part. 2 the use of xx designates silicon revision. 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see processoroperating conditions on page 25 for junction temperature (t j ) specification which is the on ly temperature specification. model 1,2 1 z = rohs compliant part. 2 for feature comparison between ADSP-BF504, adsp -bf504f, and adsp-bf506f processors, see the processor comparison in table 1 on page 3 . temperature range 3,4 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see processoroperating conditions on page 25 for junction temperature (t j ) specification which is the on ly temperature specification. 4 temperature range 0c to +70c is classified as commercial, and temperature range C40c to +85c is classified as industrial. processor instruction rate (maximum) flash memory package description package option ADSP-BF504bcpz-3f C40c to +85c 300 mhz 32m bit 88-lead lfcsp_vq cp-88-5 ADSP-BF504bcpz-4 C40c to +85c 400 mhz n/a 88-lead lfcsp_vq cp-88-5 ADSP-BF504bcpz-4f C40c to +85c 400 mhz 32m bit 88-lead lfcsp_vq cp-88-5 ADSP-BF504kcpz-3f 0c to +70c 300 mhz 32m bit 88-lead lfcsp_vq cp-88-5 ADSP-BF504kcpz-4 0c to +70c 400 mhz n/a 88-lead lfcsp_vq cp-88-5 ADSP-BF504kcpz-4f 0c to +70c 400 mhz 32m bit 88-lead lfcsp_vq cp-88-5 adsp-bf506bswz-3f C40c to +85c 300 mhz 32m bit 120-lead lqfp_ep sw-120-2 adsp-bf506bswz-4f C40c to +85c 400 mhz 32m bit 120-lead lqfp_ep sw-120-2 adsp-bf506kswz-3f 0c to +70c 300 mhz 32m bit 120-lead lqfp_ep sw-120-2 adsp-bf506kswz-4f 0c to +70c 400 mhz 32m bit 120-lead lqfp_ep sw-120-2 |
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